EVAL-ADF4360-2EB1 Analog Devices Inc, EVAL-ADF4360-2EB1 Datasheet - Page 16

• Manufacturer Part Number: EVAL-ADF4360-2EB1
• Description: BOARD EVAL EB1 FOR ADF4360-2
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADF4360-2EB1

• Module/board Type: Evaluation Board
• For Use With/related Products: ADF4360-2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

ADF4360-2
POWER-UP
Power-Up Sequence
The correct programming sequence for the ADF4360-2 after
power-up is as:
1.
2.
3.
Initial Power-Up
Initial power-up refers to programming the part after the
application of voltage to the AV
initial power-up, an interval is required between programming
the control latch and programming the N counter latch.
Table 10. C
C
10 μF
440 nF
N
Value
R counter latch
Control latch
N counter latch
N
Capacitance vs. Interval and Phase Noise
Recommended Interval Between Control Latch and N Counter Latch
≥ 5 ms
≥ 600 μs
POWER-UP
CLOCK
DATA
LE
DD
, DV
DD
LATCH DATA
R COUNTER
, V
VCO
, and CE pins. On
Figure 16. ADF4360-2 Power-Up Timing
LATCH DATA
Rev. B | Page 16 of 24
CONTROL
This interval is necessary to allow the transient behavior of the
ADF4360-2 during initial power-up to have settled. During
initial power-up, a write to the control latch powers up the part
and the bias currents of the VCO begin to settle. If these
currents have not settled to within 10% of their steady-state
value, and if the N counter latch is then programmed, the VCO
may not be able to oscillate at the desired frequency, which does
not allow the band select logic to choose the correct frequency
band and the ADF4360-2 may not achieve lock. If the
recommended interval is inserted and the N counter latch is
programmed, the band select logic can choose the correct
frequency band, and the part locks to the correct frequency.
The duration of this interval is affected by the value of the
capacitor on the C
reduce the close-in noise of the ADF4360-2 VCO. The
recommended value of this capacitor is 10 μF. Using this value
requires an interval of ≥ 5 ms between the latching in of the
control latch bits and the latching in of the N counter latch bits.
If a shorter delay is required, this capacitor can be reduced. A
slight phase noise penalty is incurred by this change, which is
explained further in Table 10.
CONTROL LATCH WRITE TO
N COUNTER LATCH WRITE
REQUIRED INTERVAL
Open-Loop Phase Noise @ 10 kHz Offset
−86 dBc
−85 dBc
N
pin (Pin 14). This capacitor is used to
LATCH DATA
N COUNTER