AD9954/PCB Analog Devices Inc, AD9954/PCB Datasheet - Page 13

• Manufacturer Part Number: AD9954/PCB
• Description: BOARD EVAL FOR AD9954
• Manufacturer: Analog Devices Inc

Specifications of AD9954/PCB

• Rohs Status: RoHS non-compliant

THEORY OF OPERATION
COMPONENT BLOCKS
REFCLK Input
The AD9954 supports several methods for generating the
internal system clock. An on-chip oscillator circuit is available
for initiating the low frequency reference signal by connecting a
crystal to the clock input pins. The system clock can be generated
using an internal, PLL-based reference clock multiplier, allowing
the part to operate with a low frequency clock source while still
providing a high sample rate for the DDS and DAC. For best
phase noise performance, a clean, stable clock with a high slew
rate should be used to drive the REFCLK pin and bypass the
multiplier.
The available modes are configured using the CLKMODESELECT
pin, CFR1<4> and CFR2<7:3>. Note that the CLKMODESELECT
pin is a 1.8 V logic only and does not apply to 3.3 V logic.
Pulling CLKMODESELECT high enables the on-chip crystal
oscillator circuit. With the on-chip oscillator enabled, users of
the AD9954 connect an external crystal to the REFCLK and
REFCLK inputs to produce a low frequency reference clock (see
Table 1 for the crystal frequency range supported). The signal
generated by the oscillator is buffered, and then delivered to the
rest of the chip. This buffered signal is provided on the
CRYSTAL OUT pin.
When the internal oscillator is disabled, an external oscillator
must provide the REFCLK and/or REFCLK signals. For differential
operation, these pins are driven with complementary signals. For
single-ended operation, a 0.1 μF capacitor should be connected
between the unused pin and the analog power supply. With the
capacitor in place, the clock input pin bias voltage is 1.35 V.
Table 5 summarizes the clock modes of operation. Note the PLL
multiplier is controlled via the CFR2<7:3> bits, independent of
the CFR1<4> bit.
Clock Multiplier
An on-board PLL allows multiplication of the REFCLK
frequency. The multiplication factor is set using CFR2<7:3>.
When programmed for values ranging from 0x04 to 0x14
(decimal 4 to 20), the PLL multiplies the REFCLK input
frequency by the programmed value. The user must consider the
specified maximum frequency for the PLL when programming. If
the multiplication factor is changed, the user must allocate time
to allow the PLL to lock (approximately 1 ms).
Table 5. Clock Input Modes of Operation
CFR1<4>
Low
Low
Low
Low
High
CLKMODESELECT
High
High
Low
Low
X
CFR2<7:3>
4 ≤ M ≤ 20
M < 4 or M > 20
4 ≤ M ≤ 20
M < 4 or M > 20
X
Rev. B | Page 13 of 40
Oscillator Enabled?
Yes
Yes
No
No
No
The PLL is bypassed by programming a value outside the range
of 4 to 20 (decimal). When bypassed, the PLL is shut down to
conserve power.
The VCO in the PLL has a selectable frequency range. Use the
VCO range bit (CFR2<2>) to set the appropriate range.
The PLL in the clock multiplier has a loop filter comprised
of on-chip components as well as external components.
Recommended values for the external resistor/capacitor
are provided in Table 4.
Table 4. External Loop Filter Components for Clock Multiplier
Multiply Value
4×
10×
20×
DAC Output
Unlike many DACs, the DAC output on the AD9954 is referenced
to AVDD, not AGND.
Two complementary outputs provide a combined full-scale
output current (I
common-mode noise that may be present at the DAC output,
resulting in a better signal-to-noise ratio. The full-scale current
is controlled by means of an external resistor (R
between the DAC_R
the exposed paddle). The full-scale current is proportional to
the resistor value by the equation
The maximum full-scale output current of the combined
DAC outputs is 15 mA. Limiting the output to 10 mA
maximum provides the best spurious-free dynamic range
(SFDR) performance. The DAC output compliance range is
AVDD + 0.5 V to AVDD − 0.5 V. Voltages developed beyond
this range result in excessive DAC distortion and could potentially
damage the DAC output circuitry. Proper attention should be
paid to the load termination to keep the output voltage within
this compliance range.
R
SET


39.19/
System Clock
f
f
f
f
f
CLK
CLK
CLK
CLK
CLK
OUT
= f
= f
= f
= f
= 0
I
). Differential outputs reduce the amount of
OUT
SET
OSC
OSC
OSC
OSC
Resistor Value
0 Ω
1 kΩ
243 Ω
pin and the DAC ground pin (Pin 49,
× M
× M

Ω
Frequency Range (MHz)
80 < f
20 < f
80 < f
10 < f
N/A
CLK
CLK
CLK
CLK
Capacitor Value (μF)
0.1
0.1
0.01
< 400
< 30
< 400
< 400
SET
) connected
AD9954