AD9952/PCB Analog Devices Inc, AD9952/PCB Datasheet - Page 5

• Manufacturer Part Number: AD9952/PCB
• Description: BOARD EVAL FOR AD9952
• Manufacturer: Analog Devices Inc
• Series: AgileRF™r
• Type: DDS (Direct Digital Synthesis)r

Specifications of AD9952/PCB

• Rohs Status: RoHS non-compliant
• Contents: Evaluation Board
• For Use With/related Products: AD9952

Parameter
CMOS LOGIC INPUTS
CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 1.8 V
CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 3.3 V
POWER CONSUMPTION (AVDD = DVDD = 1.8 V)
SYNCHRONIZATION FUNCTION
1
2
3
4
5
6
7
8
9
To achieve the best possible phase noise, the largest amplitude clock possible should be used. Reducing the clock input amplitude reduces the phase noise
performance of the device.
Represents the cycle-to-cycle residual jitter from the comparator alone.
Represents the cycle-to-cycle residual jitter from the DDS core driving the comparator.
The maximum frequency of the serial I/O port refers to the maximum speed of the port during a write operation. During a register readback, the maximum port speed
is restricted to 2 Mbps.
Setup time refers to the TCSU (setup time of the falling edge of CS to the SCLK rising edge) and TDSU (setup time of the data change on SDIO to the SCLK rising edge).
Wake-up time refers to the recovery from analog power-down modes (see the Power-Down Functions section). The longest time required is for the reference clock
multiplier PLL to relock to the reference. The wake-up time assumes there is no capacitor on DACBP and that the recommended PLL loop filter values are used.
SYSCLK cycle refers to the actual clock frequency used on-chip by the DDS. If the reference clock multiplier is used to multiply the external reference clock frequency,
the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier is not used, the SYSCLK
frequency is the same as the external reference clock frequency.
SYNC_CLK = ¼ SYSCLK rate. For SYNC_CLK rates ≥ 50 MHz, the high speed sync enable bit, CFR2 [11], should be set.
This parameter indicates that the digital synchronization feature cannot overcome phase delays (timing skew) between system clock rising edges. If the system clock
edges are aligned, the synchronization function should not increase the skew between the two edges.
Latency
Logic 1 Voltage @ DVDD_I/O (Pin 43) = 1.8 V
Logic 0 Voltage @ DVDD_I/O (Pin 43) = 1.8 V
Logic 1 Voltage @ DVDD_I/O (Pin 43) = 3.3 V
Logic 0 Voltage @ DVDD_I/O (Pin 43) = 3.3 V
Logic 1 Current
Logic 0 Current
Input Capacitance
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Voltage
Logic 0 Voltage
Single-Tone Mode
Rapid Power-Down Mode
Full-Sleep Mode
Maximum SYNC Clock Rate (DVDD_I/O = 1.8 V)
Maximum SYNC Clock Rate (DVDD_I/O = 3.3 V)
SYNC_CLK Alignment Resolution
Wake-Up Time
Minimum Reset Pulse Width High
I/O UPDATE to SYNC_CLK Setup Time DVDD_I/O = 3.3 V
I/O UPDATE to SYNC_CLK Setup Time DVDD_I/O = 3.3 V
I/O UPDATE, SYNC_CLK Hold Time
I/O UPDATE to Frequency Change Propagation Delay
I/O UPDATE to Phase Offset Change Propagation Delay
I/O UPDATE to Amplitude Change Propagation Delay
6
8
9
Rev. B | Page 5 of 28
Temp
Full
Full
Full
Full
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Min
5
4
6
0
24
24
16
1.25
2.2
1.35
2.8
62.5
100
Typ
1
3
2
162
150
20
±1
Max
0.6
0.8
12
12
0.4
0.4
171
160
27
Unit
ms
SYSCLK cycles
ns
ns
ns
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
V
V
V
V
µA
µA
pF
V
V
V
V
mW
mW
mW
MHz
MHz
SYSCLK cycles
AD9952
7