AD9760-EB Analog Devices Inc, AD9760-EB Datasheet
AD9760-EB
Specifications of AD9760-EB
Related parts for AD9760-EB
AD9760-EB Summary of contents
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... The AD9760 is available in a 28-lead SOIC and TSSOP packages specified for operation over the industrial temperature range. PRODUCT HIGHLIGHTS 1. The AD9760 is a member of the TxDAC product family that provides an upward or downward component selection path based on resolution ( bits), performance and cost. 2. Manufactured on a CMOS process, the AD9760 uses a pro- ...
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... AD9760/AD9760-50–SPECIFICATIONS DC SPECIFICATIONS ( MIN Parameter RESOLUTION 1 DC ACCURACY Integral Linearity Error (INL) Differential Nonlinearity (DNL) MONOTONICITY ANALOG OUTPUT Offset Error Gain Error (Without Internal Reference) Gain Error (With Internal Reference) 2 Full-Scale Output Current Output Compliance Range Output Resistance Output Capacitance REFERENCE OUTPUT ...
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... AD9760-50 Max Min Typ Max 2.5 2 N/A N/A N/A N N/A –73 –76 –70 –71 –68 –71 N/A AD9760 Units MSPS pA/√Hz pA/√Hz dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc ...
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... V AD9760ARU +0.3 V +6.5 V AD9760AR50 DVDD + 0.3 V DVDD + 0.3 V AD9760ARU50 –40°C to +85°C AVDD + 0.3 V AVDD + 0.3 V AD9760-EB AVDD + 0.3 V +0.3 V °C +150 THERMAL CHARACTERISTICS °C +150 Thermal Resistance 28-Lead 300 mil (7.5 mm) SOIC °C +300 θ = 71.4°C/W JA θ ...
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... PIN CONFIGURATION (MSB) DB9 1 28 CLOCK 2 DB8 27 DVDD DB7 3 26 DCOM 4 DB6 DB5 24 AVDD AD9760 DB4 6 23 COMP2 TOP VIEW (Not to Scale) DB3 OUTA DB2 OUTB 9 DB1 20 ACOM 10 19 DB0 COMP1 ADJ REFIO REFLO SLEEP CONNECT PIN FUNCTION DESCRIPTIONS –5– AD9760 ...
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... Total Harmonic Distortion THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured output signal expressed as a percentage or in decibels (dB). +5V 0.1 F REFLO COMP1 AVDD ACOM AD9760 50pF PMOS COMP2 CURRENT SOURCE ARRAY I LSB SEGMENTED SWITCHES I FOR DB11– ...
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... A – dBFS OUT Figure 10. Single-Tone SFDR vs OUT OUT CLOCK –7– AD9760 = +25 C, SFDR up to Nyquist, unless otherwise noted –6dBFS 75 –12dBFS 70 0dBFS 0.00 2.00 4.00 6.00 8.00 10.00 FREQUENCY – MHz Figure 5. SFDR vs. f ...
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... AD9760 –70 –75 2ND HARMONIC –80 3RD HARMONIC –85 4TH –90 HARMONIC – 100 120 140 FREQUENCY – MSPS Figure 12. THD vs CLOCK MHz OUT 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 0 125 250 375 500 625 750 875 ...
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... A – dBFS OUT Figure 28. Single-Tone SFDR vs OUT OUT CLOCK –9– AD9760 = +25 C, SFDR up to Nyquist, unless otherwise noted –6dBFS 75 70 –12dBFS 65 0dBFS 0.00 2.00 4.00 6.00 8.00 10.00 FREQUENCY – MHz Figure 23. SFDR vs. f ...
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... AD9760 –70 –75 2ND HARMONIC 3RD –80 HARMONIC –85 –90 4TH HARMONIC – 100 120 140 FREQUENCY – MSPS Figure 30. THD vs. f CLOCK MHz OUT 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 0 125 250 375 500 625 750 ...
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... FUNCTIONAL DESCRIPTION Figure 39 shows a simplified block diagram of the AD9760. The AD9760 consists of a large PMOS current source array that is capable of providing total current. The array is divided into 31 equal currents that make up the 5 most sig- nificant bits (MSBs). The next 4 bits or middle bits consist of 15 equal current sources whose value is 1/16th of an MSB current source ...
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... MΩ) of REFIO minimizes any loading of the external reference. and REFERENCE CONTROL AMPLIFIER OUTA The AD9760 also contains an internal control amplifier that is used to regulate the DAC’s full-scale output current, I (7) The control amplifier is configured as a V-I converter as shown and I ...
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... single-ended unipolar output is desirable, CURRENT I should be selected. OUTA SOURCE ARRAY The distortion and noise performance of the AD9760 can be enhanced when the AD9760 is configured for differential opera- tion. The common-mode error sources of both I I 625A can be significantly reduced by the common-mode rejection of a REF transformer or differential amplifier ...
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... The drivers of the digital data interface circuitry should be specified to meet the mini- mum setup and hold times of the AD9760 as well as its required min/max input logic level thresholds. Typically, the selection of the slowest logic family that satisfies the above conditions will result in the lowest data feedthrough and noise ...
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... COMP1. With a nominal value of 0.1 µF, the AD9760 takes less than 5 µs to power down and approximately 3. power back up. Note, the SLEEP MODE should not be used when the external control amplifier is used as shown in Figure 45 ...
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... In this case, AVDD which is the positive analog supply for both the AD9760 and the op amp is also used to level-shift the differ- ential output of the AD9760 to midsupply (i.e., AVDD/2). The AD8041 is a suitable op amp for this application. ...
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... Figure 55. Differential LC Filter for Single + Applications Maintaining low noise on power supplies and ground is critical to obtain optimum results from the AD9760. If properly imple- mented, ground planes can perform a host of functions on high speed circuit boards: bypassing, shielding, current transport, etc. In mixed signal design, the analog and digital portions of ...
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... QUADRATURE MODULATOR AD9760 EVALUATION BOARD General Description The AD9760- evaluation board for the AD9760 10-bit D/A converter. Careful attention to layout and circuit design, combined with a prototyping area, allow the user to easily and effectively evaluate the AD9760 in any application where high resolution, high speed conversion is required. ...
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... REV. B Figure 59. Evaluation Board Schematic –19– AD9760 ...
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... AD9760 Figure 60. Silkscreen Layer—Top Figure 61. Component Side PCB Layout (Layer 1) –20– REV. B ...
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... REV. B Figure 62. Ground Plane PCB Layout (Layer 2) Figure 63. Power Plane PCB Layout (Layer 3) –21– AD9760 ...
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... AD9760 Figure 64. Solder Side PCB Layout (Layer 4) Figure 65. Silkscreen Layer—Bottom –22– REV. B ...
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... PLANE BSC 0.0091 (0.23) (RU-28) 0.386 (9.80) 0.378 (9.60 PIN 1 0.0433 (1.10) MAX 0.0118 (0.30) 0.0256 (0.65) 0.0079 (0.20) BSC 0.0075 (0.19) 0.0035 (0.090) –23– AD9760 0.0291 (0.74) 45 0.0098 (0.25) 0.0500 (1.27 0.0157 (0.40) 0.028 (0.70 0.020 (0.50) ...