HS0005KCU04H Renesas Electronics America, HS0005KCU04H Datasheet - Page 138

EMULATOR E10A-USB SUPERH RISC

HS0005KCU04H

Manufacturer Part Number
HS0005KCU04H
Description
EMULATOR E10A-USB SUPERH RISC
Manufacturer
Renesas Electronics America
Type
In Circuit Debuggerr
Datasheet

Specifications of HS0005KCU04H

Contents
Emulation Module
For Use With/related Products
SH7205, SH7265
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
This dialog box is used to specify conditions for the acquisition of trace information.
When [I-Trace] has been selected:
[Channel 1]
[Type]
[Channel 2]
[Type]
Rev. 2.00 Nov. 19, 2009 Page 116 of 294
REJ10J1766-0200
[I-Trace mode]:
[M-Bus & Branch, CPU0]
: Set the trace acquisition conditions for channel 1. The same conditions
cannot be set for channels 1 and 2.
[I-Bus, CPU0]
[F-Bus, CPU0]
[M-Bus & Branch, CPU1]
[I-Bus, CPU1]
[F-Bus, CPU1]
[DMAC]
: Set the trace acquisition conditions for channel 2. The same conditions
cannot be set for channels 1 and 2.
[M-Bus & Branch, CPU0]
[I-Bus, CPU0]
[F-Bus, CPU0]
[M-Bus & Branch, CPU1]
[I-Bus, CPU1]
Set the bus and other conditions for acquisition of the internal trace.
: Trace information is acquired with M-bus
access and branching by CPU0 as
conditions.
: Trace information is acquired with I-bus
access by CPU0 as condition.
: Trace information is acquired with F-bus
access by CPU0 as a condition.
: Trace information is acquired with M-bus
access and branching by CPU1 as
conditions.
: Trace information is acquired with I-bus
access by CPU1 as a condition.
: Trace information is acquired with F-bus
access by CPU1 as a condition.
: Acquires trace information on access by
the DMAC.
: Trace information is acquired with M-bus
access and branching by CPU0 as
conditions.
: Trace information is acquired with I-bus
access by CPU0 as a condition.
: Trace information is acquired with F-bus
access by CPU0 as a condition.
: Trace information is acquired with M-bus
access and branching by CPU1 as
conditions.
: Trace information is acquired with I-bus
access by CPU1 as a condition.

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