MSC8156ADS Freescale Semiconductor, MSC8156ADS Datasheet - Page 39

• Manufacturer Part Number: MSC8156ADS
• Description: BOARD ADS FOR MSC8156
• Manufacturer: Freescale Semiconductor
• Type: DSPr

Specifications of MSC8156ADS

• Contents: Board
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): Yes
• For Use With/related Products: MSC8156
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.16.6.2 BCSR1 Reset Config Register 1
The BCSR1 may be read or written at any time. BCSR1 defaults are attributed at the time of
Power-On-Reset. BCSR1 reflects RCWL bits 23–16. The fields are described in Table 2-14:
2.16.6.3 BCSR2 Reset Config Register 2
The BCSR2 may be read or written at any time. BCSR2 defaults are attributed at the time of
Power-On-Reset. BCSR2 reflects RCWL bits 15-8. The fields are described in Table 2-16:
Freescale Semiconductor
BIT
BIT
0-3
4,5
0-6
6
7
7
S1P
RSRVL1819
SCLK2
SCLK1
RSRVL15-9
RSRVL8
Value (hex)
0xB–0xF
MNEMONIC
0xA
MNEMONIC
0
1
2
3
4
5
6
7
8
9
SERDES Port 1 Protocol. Four bits S1P[3:0] choose SerDes1
SerDes protocol according the Table 2-15
Reserved RCW Low bits 18,19
SerDes2 Reference Clock. When high SerDes2 reference clock is
125 MHz. If low SerDes1 reference clock is 100 MHz.
SerDes1 Reference Clock.When high SerDes1 reference clock is
125 MHz. If low SerDes2 reference clock is 100 MHz.
Table 2-14. BCSR1 RCWL bits 23–16 (Offset 1)
Port is deactivated
RapidIO 4x @ 1.25GHz
RapidIO 4x @ 2.5GHz
RapidIO 4x @ 3.125GHz
RapidIO 1x @ 3.125GHz
RapidIO 1x @ 1.25GHz,SGMII1,SGMII2
RapidIO 1x @ 2.5GHz,SGMII1,SGMII2
RapidIO 1x @ 1.25GHz,SGMII1
RapidIO 1x @ 1.25GHz,SGMII1
RapidIO 1x @ 1.25GHz,
RapidIO 1x @ 2.5GHz
Reserved
Table 2-16. BCSR2 RCWL bits 15-8 (Offset 2)
Reserved RCW Low bits 15 to 9. Not in use.
Reserved RCW Low bit 8. Not in use.
Table 2-15. SerDes Port 1 Protocol (S1P)
MSC8156ADS Reference Manual, Rev. 2.1
Function
Function
Protocol
Programming Logic (FPGA)
‘0000000’
SW4.4-1
DEF on
SW7.7
SW7.8
PRST
DEF
‘00’
‘0’
ATT.
R,W
R,W
ATT.
R,W
R,W
R,W
R,W
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