R0K561668S000BE Renesas Electronics America, R0K561668S000BE Datasheet - Page 10

• Manufacturer Part Number: R0K561668S000BE
• Description: KIT STARTER FOR H8SX/1668
• Manufacturer: Renesas Electronics America
• Series: H8®r
• Type: MCUr

Specifications of R0K561668S000BE

• For Use With/related Products: H8SX/1668
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Contents: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

H8
®
Family —
■
• Transmission and reception of
• Supports 10/100 Mbps receive/transfer
• Supports full-duplex and half-duplex modes
• Conforms to IEEE802.3u standard MII
• Magic Packet detection and
• Conforms to IEEE802.3x flow control
• Dedicated E-DMAC (DMA Controller)
• Transmit/receive frame status information
• Achieves efficient system bus utilization
• Supports single-frame/multi-buffer operation
■
• Provides v2.0 support
• Offers full-speed, 12Mbps
• Bus-powered mode or
• Up to 9 endpoints can be specified
• Four transfer modes supported:
• On-chip bus transceiver with
• Total 1280-Byte FIFO buffer
■
• Supports CAN specification 2.0B
• Bit timing compliant with ISO-11898-1
• 16 Mailbox version
• 15 programmable Mailboxes for transmit/receive
• Sleep mode for low power consumption and automatic
• Programmable receive filter mask (standard and
• Programmable CAN data rate up to 1MBit/s
• Transmit message queuing with internal priority
Ethernet/IEEE802.3 frames
(Media Independent Interface)
Wake-On-LAN (WOL) signal output
is indicated in descriptors
through use of block transfer (16-byte units)
communication
self-powered
Control, Interrupt, Bulk,
and Isochronous
option for using external transceiver
+ 1 receive-only Mailbox
recovery from sleep mode by detecting CAN bus activity
extended identifier) supported by all Mailboxes
sorting mechanism
Ethernet Hardware MAC 100/10
Universal Serial Bus
Controller Area Network (RCAN-ET)
On-chip Peripherals: Communication I/F
Peripheral address bus
Peripheral data bus
[USB operating clock]
EXIRQ0, EXIRQ1
DREQ0, DREQ1
[System clock]
Peripheral bus
control signal
[Internal bus]
EXTAL48
XTAL48
IRQ6
(16MHz)
φ
USB
[DMA internal request signal]
[Interrupt request signal]
E-DMAC
RAM
Transmit
descriptor
Receive
descriptor
PLL circuit
USB clock
generator
Interface
(x3)
1280-Byte FIFO
EP0s
EP0i
CAN interface
information
information
Descriptor
Descriptor
Transmit
peripheral
DMAC
Receive
DMAC
BCR
(48MHz)
(48MHz)
16-bit
bus
EP0o
EP1i
UDC synchronization
REC
(12MHz)
Transmit Buffer
UDC core
EP2o
Registers
EP2i
circuit
Transmit
Receive
Microprocessor
FIFO
FIFO
MCR
GSR
EP3o
Interface
EP3i
Transmit
buffer
Receive
buffer
USB Block Diagram: H8S/2215R
CAN Core
Receive Buffer
IMR
EP4o
IRR
EP4i
transceiver
Internal
MAC
Converter
EP5i
Command
status
interface
RCAN-ET Architecture
MII/RMII conversion
controller
Ethernet Hardware
Receive
[Power mode selection]
[Connection/disconnection]
[Suspend]
[Power supply]
[Data]
USD+
USD-
Control
signals
PORT
Legend:
UDC:
USB Device Controller
EP0s:
Endpoint 0 setup FIFO
EP0i to 5i:
Endpoint 0 to 5 In FIFO
EP0o to 4o:
Endpoint 0 to 4 Out FIFO
PHY
Mailbox Control
Mailbox 0 to 15
Mailbox 0 to 15
Block Diagram
UBPM
VBUS
USPND
DrVcc
DrVss
Rs
Rs
MAC 100/10
MII
(register)
(RAM)
TEC
controller
D+
Transmit
D-
signals
Status
8