DSP56L307EVM Freescale Semiconductor, DSP56L307EVM Datasheet
DSP56L307EVM
Specifications of DSP56L307EVM
Related parts for DSP56L307EVM
DSP56L307EVM Summary of contents
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DSP56L307 User’s Manual 24-Bit Digital Signal Processor DSP56L307UM/D Revision 0, March 2001 ...
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OnCE, DigitalDNA, and the DigitalDNA logo are trademarks of Motorola, Inc. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any ...
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Programming the Peripherals Enhanced Synchronous Serial Interface (ESSI) Serial Communications Interface (SCI) Enhanced Filter Coprocessor (EFCOP) Programming Reference Overview Signals/Connections Memory Configuration Core Configuration Host Interface (HI08) Triple Timer Module Bootstrap Program ...
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Overview 1 Signals/Connections 2 Memory Configuration 3 Core Configuration 4 Programming the Peripherals 5 Host Interface (HI08) 6 Enhanced Synchronous Serial Interface (ESSI) 7 Serial Communications Interface (SCI) 8 Triple Timer Module 9 Enhanced Filter Coprocessor (EFCOP) 10 Bootstrap Program ...
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Contents 1 Chapter Overview 1.1 Manual Organization ............................................................................................................. 1-2 1.2 Manual Conventions .............................................................................................................. 1-3 1.3 Features .................................................................................................................................. 1-4 1.4 DSP56300 Core ..................................................................................................................... 1-5 1.5 DSP56300 Core Functional Blocks ....................................................................................... 1-5 1.5.1 Data ALU............................................................................................................................... 1-6 1.5.1.1 Data ALU Registers......................................................................................................... 1-6 1.5.1.2 ...
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External Data Bus .................................................................................................................. 2-6 2.5.3 External Bus Control ............................................................................................................. 2-6 2.6 Interrupt and Mode Control ................................................................................................... 2-9 2.7 HI08 ..................................................................................................................................... 2-10 2.8 Enhanced Synchronous Serial Interface 0 ........................................................................... 2-13 2.9 Enhanced Synchronous Serial Interface 1 ........................................................................... 2-15 2.10 ...
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DRAM Control Register (DCR) .......................................................................................... 4-23 4.6.3 Address Attribute Registers (AAR[0–3]) ............................................................................ 4-25 4.7 DMA Control Registers 5–0 (DCR[5–0]) ........................................................................... 4-28 4.8 Device Identification Register (IDR)................................................................................... 4-34 4.9 JTAG Identification (ID) Register ....................................................................................... 4-34 4.10 JTAG Boundary Scan Register ...
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Host Port Control Register (HPCR)..................................................................................... 6-18 6.6.7 Host Transmit (HTX) Register ............................................................................................ 6-21 6.6.8 Host Receive (HRX) Register.............................................................................................. 6-22 6.6.9 DSP-Side Registers After Reset .......................................................................................... 6-22 6.7 Host Programmer Model ..................................................................................................... 6-23 6.7.1 Interface Control Register (ICR) ......................................................................................... 6-24 ...
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ESSI Transmit Data Registers (TX[2–0])............................................................................ 7-33 7.5.8 ESSI Time Slot Register (TSR) ........................................................................................... 7-33 7.5.9 Transmit Slot Mask Registers (TSMA, TSMB) .................................................................. 7-33 7.5.10 Receive Slot Mask Registers (RSMA, RSMB) ................................................................... 7-35 7.6 GPIO Signals and Registers................................................................................................. 7-36 7.6.1 ...
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Individual Timer Block Diagram........................................................................................... 9-2 9.2 Operation ............................................................................................................................... 9-3 9.2.1 Timer After Reset .................................................................................................................. 9-3 9.2.2 Timer Initialization ................................................................................................................ 9-4 9.2.3 Timer Exceptions ................................................................................................................... 9-4 9.3 Operating Modes.................................................................................................................... 9-5 9.3.1 Triple Timer Modes ............................................................................................................... 9-6 9.3.1.1 Timer GPIO (Mode ...
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Real Mode................................................................................................................ 10-9 10.3.3.1.2 Complex Mode ...................................................................................................... 10-10 10.3.3.1.3 Alternating Complex Mode ................................................................................... 10-10 10.3.3.1.4 Magnitude Mode.................................................................................................... 10-11 10.3.3.2 FIR Filter Type Processing Options ............................................................................ 10-11 10.3.3.2.1 Coefficient Update Option..................................................................................... 10-11 10.3.3.2.2 Adaptive Mode Option .......................................................................................... 10-11 10.3.3.2.3 Multichannel ...
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B Chapter Programming Reference B.1 Internal I/O Memory Map......................................................................................................B-3 B.2 Interrupt Sources and Priorities .............................................................................................B-9 B.3 Programming Sheets ............................................................................................................B-13 Index xii DSP56L307 User’s Manual ...
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Figures 1-1 DSP56L307 Block Diagram .................................................................................... 1-11 2-1 Signals Identified by Functional Group..................................................................... 2-2 3-1 Memory Switch Off, Cache Off, 24-Bit Mode ....................................................... 3-10 3-2 Memory Switch Off, Cache On, 24-Bit Mode ........................................................ 3-11 3-3 Memory Switch On (MSW = ...
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HI08 Read and Write Operations in Big Endian Mode ........................................... 6-12 6-6 Host Control Register (HCR) (X:$FFFFC2) ........................................................... 6-14 6-7 Host Status Register (HSR) (X:$FFFFC3) .............................................................. 6-15 6-8 Host Data Direction Register (HDDR) (X:$FFFFC8)............................................. 6-16 6-9 Host Data Register ...
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Timer Mode (TRM = 1)............................................................................................. 9-7 9-4 Timer Mode (TRM = 0)............................................................................................. 9-7 9-5 Pulse Mode (TRM = 1).............................................................................................. 9-8 9-6 Pulse Mode (TRM = 0).............................................................................................. 9-9 9-7 Toggle Mode, TRM = 1 ........................................................................................... 9-10 9-8 Toggle Mode, TRM ...
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B-12 Host Control Register ..............................................................................................B-24 B-13 Interrupt Control and Command Vector Registers ..................................................B-25 B-14 Interrupt Vector and Host Transmit Data Registers ................................................B-26 B-15 ESSI Control Register A (CRA) ..............................................................................B-27 B-16 ESSI Control Register B (CRB) ..............................................................................B-28 B-17 ESSI Transmit and ...
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Tables 1-1 High True/Low True Signal Conventions ................................................................. 1-3 1-2 DSP56L307 Switch Memory Configuration ............................................................. 1-9 2-1 DSP56L307 Functional Signal Groupings ................................................................ 2-1 2-1 Power Inputs .............................................................................................................. 2-3 2-1 Grounds...................................................................................................................... 2-4 2-1 Clock Signals ............................................................................................................. 2-4 2-1 Phase-Locked Loop Signals....................................................................................... ...
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Interface Control Register (ICR) Bit Definitions .................................................... 6-25 6-16 Command Vector Register (CVR) Bit Definitions.................................................. 6-27 6-17 Interface Status Register (ISR) Bit Definitions ....................................................... 6-28 6-18 Host-Side Registers After Reset .............................................................................. 6-32 6-19 HI08 Programming Model, DSP Side ..................................................................... ...
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Chapter 1 Overview This manual describes the DSP56L307 24-bit digital signal processor (DSP), its memory, operating modes, and peripheral modules. The DSP56L307 is an implementation of the DSP56300 core with a unique configuration of on-chip memory, cache, and peripherals. Use ...
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Manual Organization 1.1 Manual Organization This manual contains the following sections and appendices: Chapter 1, Overview — Features list and block diagram, related documentation, organization of this manual, and the notational conventions used. Chapter 2, Signals/Connections — DSP56L307 signals and ...
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Manual Conventions This manual uses the following conventions: Bits within registers are always listed from most significant bit (MSB) to least significant bit (LSB). Bits within a register are indicated AA[n–m], n > m, when more than one bit ...
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Features Code examples are displayed in a monospaced font, as shown in Example 1-1. Example 1-1. Sample Code Listing BFSET #$0007,X:PCC; Configure: ; MISO0, MOSI0, SCK0 for SPI master ; ~SS0 as PC3 for GPIO Hex values are indicated with ...
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DSP56300 Core Core features are fully described in the DSP56300 Family Manual. (This manual, in contrast, documents pinout, memory, and peripheral features.) Core features are as follows: 160 MIPS (290 MIPS using the EFCOP in filtering applications) with a ...
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DSP56300 Core Functional Blocks 1.5.1 Data ALU The data ALU performs all the arithmetic and logical operations on data operands in the DSP56300 core. These are the components of the data ALU: Fully pipelined 24 24-bit parallel multiplier-accumulator Bit field ...
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Address Generation Unit (AGU) The AGU performs the effective address calculations using integer arithmetic necessary to address data operands in memory and contains the registers that generate the addresses. It implements four types of arithmetic: linear, modulo, multiple wrap-around ...
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DSP56300 Core Functional Blocks On-chip memory-expandable hardware stack Nested hardware DO loops Fast auto-return interrupts Hardware system stack The PCU uses the following registers: Program counter register Status register Loop address register Loop counter register Vector base address register Size ...
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JTAG TAP and OnCE Module In the DSP56300 core is a dedicated user-accessible TAP that is fully compatible with the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture . Problems with testing high-density circuit boards led to ...
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Internal Buses 1.5.7 Off-Chip Memory Expansion Memory can be expanded off chip to the following capacities: Data memory expansion to two 256 K 24-bit word memory spaces using standard address lines Program memory expansion to one 256 K 24-bit word ...
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Block Diagram All internal buses on the DSP56300 family members are 24-bit buses. The program data bus is also a 24-bit bus. Figure 1-1 shows a block diagram of the DSP56L307 SCI Triple Host Interface Interface Timer ...
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DMA 1.8 DMA The DMA block has the following features: Six DMA channels supporting internal and external accesses One-, two-, and three-dimensional transfers (including circular buffering) End-of-block-transfer interrupts Triggering from interrupt lines and all peripherals 1.9 Peripherals In addition to ...
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DSP core communication with the HI08 registers using standard instructions and addressing modes. 1.9.3 ESSI The DSP56L307 provides two independent and identical ESSIs. Each ESSI has a full-duplex serial port for communication with a variety of serial devices, including ...
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Peripherals 1.9.5 Timer Module The triple timer module is composed of a common 21-bit prescaler and three independent and identical general-purpose 24-bit timer/event counters, each with its own memory-mapped register set. Each timer has the following properties: A single signal ...
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Chapter 2 Signals/Connections The DSP56L307 input and output signals are organized into functional groups as shown in Table 2-1. Figure 2-1 diagrams the DSP56L307 signals by functional group. The remainder of this chapter describes the signal pins in each functional ...
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Power Inputs: V PLL CCP 4 V Core Logic CCQL 3 V I/O CCQH 3 V Address Bus CCA 4 V Data Bus CCD 2 V Bus Control CCC V HI08 CCH 2 V ESSI/SCI/Timer CCS Grounds: GND PLL P ...
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Power Power Name V PLL Power—V CCP should be provided with an extremely low impedance path to the V V Quiet Core (Low) Power—An isolated power for the DSP56300 core processing logic. This CCQL input must be isolated externally ...
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Ground 2.2 Ground Ground Name GND PLL Ground—Ground-dedicated for PLL use. The connection should be provided with an extremely P low-impedance path to ground. V close as possible to the chip package. GND PLL Ground 1—Ground-dedicated for PLL use. The ...
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PLL State During Signal Name Type PCAP Input Input CLKOUT Output Chip-driven PINIT Input Input NMI Input Table 2-1. Phase-Locked Loop Signals Reset PLL Capacitor—Connects an off-chip capacitor to the PLL filter. Connect one capacitor terminal to PCAP and ...
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External Memory Expansion Port (Port A) 2.5 External Memory Expansion Port (Port A) Note: When the DSP56L307 enters a low-power standby mode (stop or wait), it releases bus mastership and tri-states the relevant Port A signals: A[0–17], D[0–23], AA0/RAS0–AA3/RAS3, RD, ...
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Table 2-3. External Bus Control Signals (Continued) State During Signal Name Type Reset WR Output Tri-stated TA Input Ignored Input BR Output Output (deasserted) BG Input Ignored Input External Memory Expansion Port (Port A) Signal Description Write Enable—When the DSP ...
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External Memory Expansion Port (Port A) Table 2-3. External Bus Control Signals (Continued) State During Signal Name Type Reset BB Input/ Input Output CAS Output Tri-stated BCLK Output Tri-stated BCLK Output Tri-stated 2-8 Signal Description Bus Busy—Indicates that the bus ...
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Interrupt and Mode Control The interrupt and mode control signals select the chip’s operating mode as it comes out of hardware reset. After RESET is deasserted, these inputs are hardware interrupt request lines. Table 2-4. Interrupt and Mode Control ...
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HI08 2.7 HI08 The HI08 provides a fast, 8-bit, parallel data port that connects directly to the host bus. The HI08 supports a variety of standard buses and can directly connect to a number of industry-standard microcomputers, microprocessors, DSPs, and ...
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Table 2-5. Host Interface (Continued) State During Signal Name Type Reset or Stop HA2 Input Disconnected internally HA9 Input PB10 Input or Output HRW Input Disconnected internally HRD/HRD Input PB11 Input or Output HDS/HDS Input Disconnected internally HWR/HWR Input PB12 ...
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HI08 Table 2-5. Host Interface (Continued) State During Signal Name Type Reset or Stop HREQ/HREQ Output Disconnected internally HTRQ/HTRQ Output PB14 Input or Output HACK/HACK Input Disconnected internally HRRQ/HRRQ Output PB15 Input or Output Note: 1. The Wait processing state ...
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Enhanced Synchronous Serial Interface 0 There are two synchronous serial interfaces (ESSI0 and ESSI1) that provide a full-duplex serial port for serial communication with a variety of serial devices, including one or more industry-standard codecs, other DSPs, microprocessors, and ...
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Enhanced Synchronous Serial Interface 0 Table 2-6. Enhanced Synchronous Serial Interface 0 (ESSI0) (Continued) State During Signal Type Name Reset SCK0 Input/Output Input PC3 Input or Output SRD0 Input Input PC4 Input or Output STD0 Output Input PC5 Input or ...
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Enhanced Synchronous Serial Interface 1 Table 2-7. Enhanced Synchronous Serial Interface 1 (ESSI1) State During Signal Type Name Reset SC10 Input or Input Output PD0 SC11 Input/Output Input PD1 Input or Output SC12 Input/Output Input PD2 Input or Output ...
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Enhanced Synchronous Serial Interface 1 Table 2-7. Enhanced Synchronous Serial Interface 1 (ESSI1) (Continued) State During Signal Type Name Reset SCK1 Input/Output Input PD3 Input or Output SRD1 Input Input PD4 Input or Output STD1 Output Input PD5 Input or ...
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SCI The SCI provides a full duplex port for serial communication to other DSPs, microprocessors, or peripherals such as modems. Table 2-8. Serial Communication Interface (SCI) State During Signal Type Name Reset RXD Input Input PE0 Input or Output ...
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Timers 2.11 Timers Three identical and independent timers are implemented in the DSP56L307. Each timer can use internal or external clocking and can either interrupt the DSP56L307 after a specified number of events (clocks) or signal an external device after ...
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JTAG and OnCE Interface The DSP56300 family and in particular the DSP56L307 support circuit-board test strategies that are based on the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture, the industry standard developed under the sponsorship of ...
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JTAG and OnCE Interface 2-20 DSP56L307 User’s Manual ...
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Chapter 3 Memory Configuration Like all members of the DSP56300 core family, the DSP56L307 can address three sets 24-bit memory internally: program, X data, and Y data. Each of these memory spaces includes both on-chip and external ...
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Program Memory Space 3.1.1 Internal Program Memory The default on-chip program memory consists of a 24-bit-wide, high-speed, SRAM occupying the lowest 16 K locations ($0–$3FFF) in program memory space. The on-chip program RAM is organized in 16 banks with 1024 ...
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MSW[1–0] = 10—The 8 K higher locations ($4000–$5FFF) of the internal X data memory and the 8 K higher locations ($4000–$5FFF) of the internal Y data memory are switched to internal program memory. In such a case, the on-chip ...
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X Data Memory Space 3.2 X Data Memory Space The X data memory space consists of the following: Internal X data memory ( default down Internal X I/O space (upper 128 locations) Optional off-chip memory ...
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The lowest external X memory location is $6000. — MSW[1–0] = 10—The 8 K higher locations ($4000–$5FFF) of the internal X memory are switched to internal program memory, and therefore the ...
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Y Data Memory Space 3.3 Y Data Memory Space The Y data memory space consists of the following: Internal Y data memory ( default down Internal Y I/O space (16 locations—$FFFF80–$FFFF8F) External Y I/O space ...
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The lowest external Y memory location is $6000. — MSW[1–0] = 10—The 8 K higher locations ($4000–$5FFF) of the internal Y memory are switched to internal program memory, and therefore the ...
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Dynamic Memory Configuration Switching 3.3.4 External Y I/O Space Off-chip peripheral registers should be mapped into the top 64 locations ($FFFFC0–$FFFFFF) to take advantage of the move peripheral data (MOVEP) instruction and the bit-oriented instructions (BCHG, BCLR, BSET, BTST, BRCLR, ...
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Sixteen-Bit Compatibility Mode Configuration The sixteen-bit compatibility (SC) mode allows the DSP56L307 to use DSP56000 object code without change. The SC bit (Bit 13 in the SR) is used to switch from the default 24-bit mode to this special ...
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Memory Maps Program $FFFFFF Internal Reserved $FF00C0 Bootstrap ROM $FF0000 External $004000 Internal Program RAM 16 K $000000 Bit Settings MSW Program RAM [1–0] 0 any value $0000–$3FFF Note: Lowest ...
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Program $FFFFFF Internal Reserved $FF00C0 Bootstrap ROM $FF0000 External $004000 Internal Program RAM 15 K $000400 External $000000 Bit Settings MSW Program RAM [1–0] 0 any value $0400–$3FFF Note: Lowest ...
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Memory Maps Program $FFFFFF Internal Reserved $FF00C0 Bootstrap ROM $FF0000 External $00C000 Internal Program RAM 48 K $000000 Bit Settings MSW Program RAM [1– $0000–$BFFF Note: Lowest ...
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Program $FFFFFF Internal Reserved $FF00C0 Bootstrap ROM $FF0000 External $00C000 Internal Program RAM 47 K $000400 External $000000 Bit Settings MSW Program RAM [1– $0400–$BFFF Note: Lowest ...
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Memory Maps Program $FFFFFF Internal Reserved $FF00C0 Bootstrap ROM $FF0000 External $00C000 Reserved $00A000 Internal Program RAM 40 K $000000 Bit Settings MSW Program RAM [1– $0000–$9FFF Note: Lowest ...
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Program $FFFFFF Internal Reserved $FF00C0 Bootstrap ROM $FF0000 External $00C000 Reserved $00A000 Internal Program RAM 39K $000400 External $000000 Bit Settings MSW Program RAM [1– 39K $0400–$9FFF Note: Lowest ...
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Memory Maps Program $FFFFFF Internal Reserved $FF00C0 Bootstrap ROM $FF0000 External $00C000 Reserved $008000 Internal Program RAM 32K $000000 Bit Settings MSW Program RAM [1– $0000–$7FFF Note: Lowest data ...
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Program $FFFFFF Internal Reserved $FF00C0 Bootstrap ROM $FF0000 External $00C000 Reserved $008000 Internal Program RAM 31K $000400 External $000000 Bit Settings MSW Program RAM [1– 31K $0400–$7FFF Note: Lowest ...
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Memory Maps Program $FFFFFF Internal Reserved $FF00C0 Bootstrap ROM $FF0000 External $00C000 Reserved $006000 Internal Program RAM 24 K $000000 Bit Settings MSW Program RAM [1– $0000–$5FFF Note: Lowest ...
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Program $FFFFFF Internal Reserved $FF00C0 Bootstrap ROM $FF0000 External $00C000 Reserved $006000 Internal Program RAM 23 K $000400 External $000000 Bit Settings MSW Program RAM [1– $0400–$5FFF Note: Lowest 4 K ...
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Memory Maps Program $FFFF External $4000 Internal Program RAM 16K $0000 Bit Settings MSW Program RAM [1–0] 0 any 0 1 value $0000–$3FFF Note: Lowest data RAM and data ...
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Program $FFFF External $4000 Internal Program RAM 15 K $0400 External $0000 Bit Settings MSW Program RAM [1–0] 0 any value $0400–$3FFF Note: Lowest data RAM and 4 K ...
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Memory Maps Program $FFFF External $C000 Internal Program RAM 48 K $0000 Bit Settings MSW Program RAM [1– $0000–$BFFF Note: Lowest data RAM and data ...
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Program $FFFF External $C000 Internal Program RAM 47 K $0400 External $0000 Bit Settings MSW Program RAM [1– $0400–$BFFF Note: Lowest data RAM and ...
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Memory Maps Program $FFFF External $A000 Internal Program RAM 40 K $0000 Bit Settings MSW Program RAM [1– $0000–$9FFF Note: Lowest data RAM and data ...
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Program $FFFF External $A000 Internal Program RAM 39K $0400 External $0000 Bit Settings MSW Program RAM [1– 39K $0400–$9FFF Note: Lowest data RAM and data ...
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Memory Maps Program $FFFF External $8000 Internal Program RAM 32K $0000 Bit Settings MSW Program RAM [1– $0000–$7FFF Note: Lowest data RAM and data RAM ...
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Program $FFFF External $8000 Internal Program RAM 31K $0400 External $0000 Bit Settings MSW Program RAM [1– $0400–$7FFF Note: Lowest data RAM and data RAM ...
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Memory Maps Program $FFFF External $6000 Internal Program RAM 24 K $0000 Bit Settings MSW Program RAM [1– $0000–$5FFF Note: Lowest data RAM and data ...
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Program $FFFF External $6000 Internal Program RAM 23 K $0400 External $0000 Bit Settings MSW Program RAM [1– $0400–$5FFF Note: Lowest data RAM and ...
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Memory Maps 3-30 DSP56L307 User’s Manual ...
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Chapter 4 Core Configuration This chapter presents DSP56300 core configuration details specific to the DSP56L307. These configuration details include the following: n Operating modes n Bootstrap program n Central Processor registers — Status register (SR) — Operating mode register (OMR) ...
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Operating Modes 4.1 Operating Modes The DSP56L307 begins operation by leaving the Reset state and going into one of eight operating modes. As the DSP56L307 exits the Reset state, it loads the values of MODA, MODB, MODC, and MODD into ...
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Table 4-1. DSP56L307 Operating Modes (Continued) Mode MODD MODC MODB Reset MODA Vector 1 $FF0000 Bootstrap ...
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Bootstrap Program Table 4-1. DSP56L307 Operating Modes (Continued) Mode MODD MODC MODB 4.2 Bootstrap Program The bootstrap program is factory-programmed in an internal 192-word by 24-bit bootstrap ROM located in program memory space at locations $FF0000–$FF00BF. ...
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Central Processor Unit (CPU) Registers There are two CPU registers that must be configured to initialize operation. The Status Register (SR) selects various arithmetic processing protocols and contains several status reporting flag bits. The Operating Mode Register (OMR) configures ...
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Central Processor Unit (CPU) Registers Extended Mode Register (EMR CP[1– Reset Reserved bit. Read as zero; write ...
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Table 4-2. Status Register Bit Definitions (Continued) Bit Number Bit Name Reset Value Central Processor Unit (CPU) Registers Description Reserved. Write to zero for future compatibility. ...
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Central Processor Unit (CPU) Registers Table 4-2. Status Register Bit Definitions (Continued) Bit Number Bit Name Reset Value 11–10 S[1–0] 4-8 0 Sixteen-Bit Compatibility Mode Affects addressing functionality, enabling full compatibility with object code written for the ...
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Table 4-2. Status Register Bit Definitions (Continued) Bit Number Bit Name Reset Value 9–8 I[1– Central Processor Unit (CPU) Registers Description Interrupt Mask Reflect the current Interrupt Priority Level (IPL) ...
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Central Processor Unit (CPU) Registers Table 4-2. Status Register Bit Definitions (Continued) Bit Number Bit Name Reset Value 4.3.2 Operating Mode Register (OMR) The OMR is a read/write register divided ...
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MOVEC, that specify OMR as a destination). The Stack Control/Status (SCS) byte is referenced implicitly by some instructions, such as DO, JSR, and RTI, or directly by the MOVEC instruction. During processor reset, the chip ...
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Central Processor Unit (CPU) Registers Table 4-3. Operating Mode Register (OMR) Bit Definitions (Continued) Bit Number Bit Name Reset Value 14 APD 13 ABE 12 BRT 11 TAS 10 BE 4-12 0 Address Attribute Priority Disable Disables the priority assigned ...
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Table 4-3. Operating Mode Register (OMR) Bit Definitions (Continued) Bit Number Bit Name Reset Value 9–8 CDP[1– EBD 3–0 MD–MA * The MD–MA bits reflect the corresponding value of the mode input (that is, ...
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Configuring Interrupts 4.4 Configuring Interrupts DSP56L307 interrupt handling, like that for all DSP56300 family members, is optimized for DSP applications. Refer to the sections describing interrupts in Chapter 2, Core Architecture Overview, in the DSP56300 Family Manual. Two registers are ...
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T0L1 T0L0 Reserved bit; read as zero; write with zero for future compatibility Figure 4-4. Interrupt Priority Register-Peripherals (IPRP) (X:$FFFFFE) The DSP56L307 has a four-level interrupt priority structure. Each interrupt has two ...
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Configuring Interrupts 4.4.2 Interrupt Table Memory Map Each interrupt is allocated two instructions in the interrupt table, resulting in 128 table entries for interrupt handling. Table 4-5 shows the table entry address for each interrupt source. The DSP56L307 initialization program ...
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Table 4-5. Interrupt Sources (Continued) Interrupt Interrupt Priority Level Starting Address Range VBA:$32 0–2 VBA:$34 0–2 VBA:$36 0–2 VBA:$38 0–2 VBA:$3A 0–2 VBA:$3C 0–2 VBA:$3E 0–2 VBA:$40 0–2 VBA:$42 0–2 VBA:$44 0–2 VBA:$46 0–2 VBA:$48 0–2 VBA:$4A 0–2 VBA:$4C 0–2 ...
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Configuring Interrupts 4.4.3 Processing Interrupt Source Priorities Within an IPL If more than one interrupt request is pending when an instruction executes, the interrupt source with the highest IPL is serviced first. When several interrupt requests with the same IPL ...
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Table 4-6. Interrupt Source Priorities Within an IPL (Continued) Priority ESSI1 RX data with exception interrupt ESSI1 RX data interrupt ESSI1 receive last slot interrupt ESSI1 TX data with exception interrupt ESSI1 transmit last slot interrupt ESSI1 TX data interrupt ...
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Bus Interface Unit (BIU) Registers Table 4-7. PLL Control Register (PCTL) Bit Definitions Bit Number Bit Name Reset Value 23–20 PD[3– COD 0 18 PEN Set to PINIT input value 17 PSTP 0 16 XTLD 0 15 XTLR ...
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Bus Control Register The Bus Control Register (BCR), depicted in Figure 4- read/write register that controls the external bus activity and Bus Interface Unit (BIU) operation. All BCR bits except bit 21, BBS, are read/write bits. The ...
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Bus Interface Unit (BIU) Registers Table 4-8. Bus Control Register (BCR) Bit Definitions (Continued) Bit Bit Name Reset Value Number 15–13 BA3W[2–0] 111 (7 wait states) 12–10 BA2W[2–0] 111 (7 wait states) 9–5 BA1W[4–0] 11111 (31 wait states) 4–0 BA0W[4–0] ...
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DRAM Control Register (DCR) The DRAM controller is an efficient interface to dynamic RAM devices in both random read/write cycles and Fast Access mode (Page mode). An on-chip DRAM controller controls the page hit circuit, the address multiplexing (row ...
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Bus Interface Unit (BIU) Registers Table 4-9. DRAM Control Register (DCR) Bit Definitions (Continued) Bit Reset Bit Name Number Value 14 BSTR 0 Bus Software Triggered Reset Generates a software-triggered refresh request. When BSTR is set, a refresh request is ...
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Table 4-9. DRAM Control Register (DCR) Bit Definitions (Continued) Bit Reset Bit Name Number Value 9–8 BPS[1–0] 0 Bus DRAM Page Size Defines the size of the external DRAM page and thus the number of the column address bits. The ...
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Bus Interface Unit (BIU) Registers BAC11 BAC10 BAC9 BAC8 BNC3 BNC2 BNC1 BNC0 Reserved bit. Read as zero; write to zero for future compatibility Figure 4-8. Address Attribute Registers (AAR[0–3]) (X:$FFFFF9–$FFFFF6) Table ...
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Table 4-10. Address Attribute Registers (AAR[0–3]) Bit Definitions Bit Reset Bit Name Number Value 5 BYEN 0 Bus Y Data Memory Enable A read/write control bit that enables/disables the AA pin and logic during external Y data space accesses. When ...
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DMA Control Registers 5–0 (DCR[5–0]) 4.7 DMA Control Registers 5–0 (DCR[5–0]) The DMA Control Registers (DCR[5–0]) are read/write registers that control the DMA operation for each of their respective channels. All DCR bits are cleared during processor reset ...
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Table 4-11. DMA Control Register (DCR) Bit Definitions (Continued) Bit Reset Bit Name Number Value 21–19 DTM[2–0] 0 DMA Transfer Mode Specify the operating modes of the DMA channel, as follows: DTM[2–0] 000 001 010 011 100 101 110 111 ...
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DMA Control Registers 5–0 (DCR[5–0]) Table 4-11. DMA Control Register (DCR) Bit Definitions (Continued) Bit Reset Bit Name Number Value 18–17 DPR[1–0] 0 DMA Channel Priority Define the DMA channel priority relative to the other DMA channels and to the ...
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Table 4-11. DMA Control Register (DCR) Bit Definitions (Continued) Bit Reset Bit Name Number Value DPR[1–0] 18–17 OMR - CDP[1–0] cont DMA priority > core priority (for example, if CDP = 01, or CDP = 00 and DPR ...
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DMA Control Registers 5–0 (DCR[5–0]) Table 4-11. DMA Control Register (DCR) Bit Definitions (Continued) Bit Reset Bit Name Number Value 15–11 DRS[4–0] 0 DMA Request Source Encodes the source of DMA requests that trigger the DMA transfers. The DMA request ...
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Table 4-11. DMA Control Register (DCR) Bit Definitions (Continued) Bit Reset Bit Name Number Value 10 D3D 0 Three-Dimensional Mode Indicates whether a DMA channel is currently using three-dimensional (D3D = 1) or non-three-dimensional (D3D = 0) addressing modes. The ...
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Device Identification Register (IDR) 4.8 Device Identification Register (IDR) The IDR is a read-only factory-programmed register that identifies DSP56300 family members. It specifies the derivative number and revision number of the device. This information is used in testing or by ...
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Chapter 5 Programming the Peripherals When peripherals are programmed in a given application, a number of possible modes and options are available for use. Chapters 6 through 10 describe in detail the possible modes and configurations for peripheral registers and ...
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Mapping the Control Registers 5.2 Mapping the Control Registers The I/O peripherals are controlled through registers mapped to the top 128 words of X-data memory ($FFFF80–$FFFFFF). Referred to as the internal I/O space, the control registers are accessed by move ...
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Data Transfer Methods Peripheral I/O on the DSP56L307 can be accomplished in three ways: n Polling n Interrupts n DMA 5.4.1 Polling Polling is the easiest method for data transfers. When polling is chosen, the DSP56L307 core continuously checks ...
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Data Transfer Methods When an interrupt occurs, the core execution flow jumps to the interrupt start address defined in Table B-4 in Appendix B, Programming Reference. It executes code starting at the interrupt address short interrupt ...
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DMA The Direct Memory Access (DMA) controller permits data transfers between internal/external memory and/or internal/external I/O in any combination without the intervention of the DSP56L307 core. Dedicated DMA address and data buses and internal memory partitioning ensure that a ...
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General-Purpose Input/Output (GPIO) 5.4.4 Advantages and Disadvantages Polling is the easiest method to implement, but it requires a large amount of DSP56L307 core processing power. The core cannot be involved in other processing activities while it is polling receive and ...
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DSP56303 Host Interface (HI08) Port 5.5.2 Port C Signals and Registers Each of the six Port C signals not used as an ESSI0 signal can be configured as a GPIO signal. Three registers control the GPIO functionality of Port C: ...
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General-Purpose Input/Output (GPIO) 5.5.3 Port D Signals and Registers Each of the six Port D signals not used as an ESSI1 signal can be configured as a GPIO signal. Three registers control the GPIO functionality of Port D: Port D ...
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Chapter 6 Host Interface (HI08) The host interface (HI08 byte-wide, full-duplex, double-buffered parallel port that can connect directly to the data bus of a host processor. The HI08 supports a variety of buses and provides glueless connection with ...
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Features 6.1.2 Host Processor Interface n Sixteen signals support non-multiplexed or multiplexed buses: — / host data bus ( H[0–7] HAD[0– HAD[0–7] — / address strobe ( HAS HA0 — / host address line ( HA8 HA1 — ...
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Dedicated interrupts: — Separate request lines for each interrupt source — Special host commands force DSP core interrupts under host processor control. These commands are useful for — Real-time production diagnostics — Creation of a debugging window for program ...
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Overview Table 6-2. HI08 Data Strobe Signals HI08 Port Single Strobe Mode Signal HRW/HRD HDS/HWR HDS/HDS Table 6-3. HI08 Host Request Signals HI08 Port Single Host Request Mode Signal HREQ/ HREQ/HREQ HTRQ HACK/ HACK/HACK HRRQ The HI08 port can operate ...
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DSP-side transmit path. The Receive (RXH:RXM:RXL) and Transmit Data Registers (TXH:TXM:TXL) use the same host address. During host writes to these addresses, the data is transferred to the ...
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Operation 6.4 Operation The HI08 is a slave-only device, so the host is the master of all bus transfers. In host-to-DSP transfers, the host writes data to the Transmit Data Registers (TXH:TXM:TXL). In DSP-to-host transfers the host reads data from ...
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The transfers described here occur asynchronously between the host and the DSP; each transferring data at its own pace. However, use of the appropriate handshaking protocol allows data transfers to occur at optimum rates. 6.4.1 Software ...
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Operation 6.4.2 Core Interrupts and Host Commands The HI08 can request interrupt service from the DSP56L307 core. The DSP56L307 core interrupts are internal and do not require the use of an external interrupt signal. When the appropriate interrupt enable bit ...
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However, this flexibility is independent of the data transfer mechanisms in the HI08 and allows the host to force execution of any interrupt handler (for example, SSI, SCI, IRQx, and so on). To ...
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Operation 6.4.4 Host Requests A set of signal lines allow the HI08 to request service from the host. The request signal lines normally connect to the host interrupt request pins (IRQx) and indicate to the host when the DSP HI08 ...
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Table 6-6 shows the operation of the transmit request ( lines with dual host requests enabled. Table 6-6. HTRQ and HRRQ Pin Operation In Double Request Mode (ICR[2]=HDRQ=1) ICR[1]=TREQ ICR[0]=RREQ 6.4.5 Endian ...
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Boot-up Using the HI08 Host Port A similar operation occurs when the HI08 is initialized in Big Endian mode by clearing the Host Little Endian bit (ICR[5]=HLEND). Big Endian mode is depicted in Figure 6-5. HTX/HRX Register: 23 DSP side ...
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The bootstrap program then expects the following data sequence when the user program is downloaded from the HI08: 1. Three bytes (least significant byte first) indicating the number of 24-bit program words to be loaded. 2. Three bytes (least significant ...
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DSP Core Programming Model 6.6.1 Host Control Register (HCR) This read/write register controls the HI08 interrupt operation. Initialization values for HCR bits are presented in Section 6.6.9, DSP-Side Registers After Reset, on page 6-22 —Reserved ...
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Host Status Register (HSR) The HSR is a 16-bit read-only status register by which the DSP reads the HI08 status and flags. The host processor cannot access it directly. The initialization values for the HSR bits are discussed in ...
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DSP Core Programming Model 6.6.3 Host Data Direction Register (HDDR) The HDDR controls the direction of the data flow for each of the HI08 signals configured as GPIO. Even when the HI08 functions as the host interface, its unused signals ...
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Host Base Address Register (HBAR) In multiplexed bus modes, HBAR selects the base address where the host-side registers are mapped into the host bus address space. The address from the host bus is compared with the base address as ...
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DSP Core Programming Model 6.6.6 Host Port Control Register (HPCR) The HPCR is a read/write control register that controls the HI08 operating mode. HPCR bit initialization values are discussed in Section 6.6.9, DSP-Side Registers After Reset, on page 6-22. Hardware ...
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Table 6-12. Host Port Control Register (HPCR) Bit Definitions (Continued) Bit Number Bit Name Reset Value 12 HDDS 0 11 HMUX 0 10 HASP 0 9 HDSP 0 8 HROD HEN 0 Description Host Dual Data ...
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DSP Core Programming Model Table 6-12. Host Port Control Register (HPCR) Bit Definitions (Continued) Bit Number Bit Name Reset Value 5 HAEN 4 HREN 3 HCSEN 2 HA9EN 1 HA8EN 0 HGEN 6-20 0 Host Acknowledge Enable Controls the HACK ...
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HRW HDS In a single-strobe mode (data strobe) signal qualifies the access, while a R/W (Read-Write) signal specifies the direction of the access. Data HWR Write Cycle Data HRD Read Cycle In dual-strobe mode, separate HRD and HWR ...
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DSP Core Programming Model 6.6.8 Host Receive (HRX) Register The HRX register is used in host-to-DSP data transfers. The DSP56L307 views 24-bit read-only register. Its address is X:$FFFFC6 loaded with 24-bit data from the transmit ...
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Host Programmer Model The HI08 provides a simple, high-speed interface to a host processor. To the host bus, the HI08 appears to be eight byte-wide registers. Separate transmit and receive data paths are double-buffered to allow the DSP core ...
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Host Programmer Model locations), force interrupt handlers (for example, ESSI, SCI, and perform control or debugging operations. Note: When the DSP enters Stop mode, the HI08 signals are electrically disconnected internally, thus disabling the HI08 until the core leaves stop ...
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Table 6-15. Interface Control Register (ICR) Bit Definitions Bit Number Bit Name Reset Value 7 INIT HLEND 0 4 HF1 0 3 HF0 0 2 HDRQ 0 Description Initialize The host processor uses the INIT bit ...
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Host Programmer Model Table 6-15. Interface Control Register (ICR) Bit Definitions (Continued) Bit Number Bit Name Reset Value 1 TREQ 0 RREQ 6-26 0 Transmit Request Enable Enables host requests via the host request (HREQ or HTRQ) signal when the ...
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Command Vector Register (CVR) The host processor uses the CVR, an 8-bit read/write register, to cause the DSP56L307 to execute an interrupt. The host command feature is independent of any of the data transfer mechanisms in the HI08. It ...
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Host Programmer Model 6.7.3 Interface Status Register (ISR) The host processor uses the ISR, an 8-bit read-only status register, to interrogate the HI08 status and flags. The DSP core cannot address the ISR. 7 HREQ —Reserved bit; read as 0; ...
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Table 6-17. Interface Status Register (ISR) Bit Definitions (Continued) Bit Number Bit Name Reset Value 2 TRDY 1 1 TXDE 1 0 RXDF 0 Description Transmitter Ready Indicates that TXH:TXM:TXL and the HRX registers are empty. If TRDY is set, ...
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Host Programmer Model 6.7.4 Interrupt Vector Register (IVR) The IVR is an 8-bit read/write register that typically contains the interrupt vector number used with MC68000 family processor vectored interrupts. Only the host processor can read and write this register. The ...
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Transmit Data Registers (TXH:TXM:TXL) The host processor views the transmit byte registers as three 8-bit write-only registers. These registers are the transmit high register (TXH), the transmit middle register (TXM), and the transmit low register (TXL). These registers send ...
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Host Programmer Model 6.7.7 Host-Side Registers After Reset Table 6-18 shows the result of the four kinds of reset on bits in each of the HI08 registers seen by the host processor. To cause a hardware reset, assert the software ...
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Programming Model Quick Reference Table 6-19 summarizes the HI08 programming model. Table 6-19. HI08 Programming Model, DSP Side Register Bit Bit Name No. HCR 0 HRIE Receive Interrupt Enable 1 HTIE Transmit Interrupt Enable 2 HCIE Host Command Interrupt ...
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Programming Model Quick Reference Table 6-19. HI08 Programming Model, DSP Side (Continued) Register Bit Bit Name No. 8 HROD Host Request HPCR Open Drain 9 HDSP Host Data Strobe Polarity 10 HASP Host Address Strobe Polarity 11 HMUX Host Multiplexed ...
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Table 6-20. HI08 Programming Model: Host Side Reg # ICR 0 RREQ Receive Request Enable 1 TREQ Transmit Request Enable 2 HDRQ Double Host Request 3 HF0 Host Flag 0 4 HF1 Host Flag 1 5 HLEND Host Little Endian ...
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Programming Model Quick Reference 6-36 DSP56L307 User’s Manual ...
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Chapter 7 Enhanced Synchronous Serial Interface (ESSI) The ESSI provides a full-duplex serial port for serial communication with a variety of serial devices, including one or more industry-standard codecs, other DSPs, microprocessors, and peripherals. The ESSI consists of independent transmitter ...
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ESSI Enhancements Note: This synchronous interface should not be confused with the asynchronous channels mode of the ESSI, in which separate clocks are used for the receiver and transmitter. In that mode, the ESSI is still a synchronous device because ...
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ESSI Data and Control Signals Three to six signals are required for ESSI operation, depending on the operating mode selected. The serial transmit data ( fully synchronized to the clock if they are programmed as transmit-data signals. 7.2.1 Serial ...
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ESSI Data and Control Signals 7.2.4 Serial Control Signal (SC0) ESSI0: SC00; ESSI1: SC10 To determine the function of the mode, according to Table 7-2. In Asynchronous mode, this signal is used for the receive clock I/O. In Synchronous mode, ...
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Table 7-2. Mode and Signal Definitions Control Bits SYN TE0 TE1 TE2 ...
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Operation 7.2.6 Serial Control Signal (SC2) ESSI0:SC02; ESSI1:SC12 is a frame sync I/O signal for both the transmitter and receiver in Synchronous mode and SC2 for the transmitter only in Asynchronous mode. The direction of this signal is determined by ...
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ESSI, use an ESSI individual reset when you change the ESSI control registers (except for bits TEIE, REIE, TLIE, RLIE, TIE, RIE, TE2, TE1, TE0, and RE). Here is an example of how to initialize the ESSI. 1. Put the ...
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Operation n ESSI receive last slot interrupt: Occurs when the ESSI is in Network mode and the last slot of the frame has ended. This interrupt is generated regardless of the receive mask register setting. The receive last slot interrupt ...
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To configure an ESSI exception, perform the following steps: 1. Configure the interrupt service routine (ISR): a. Load vector base address register b. Define I_VEC to be equal to the VBA value (if that is nonzero defined, ...
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Operating Modes: Normal, Network, and On-Demand 7.4 Operating Modes: Normal, Network, and On-Demand The ESSI has three basic operating modes and several data and operation formats. These modes are programmed via the ESSI control registers. The data and operation formats ...
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Synchronous/Asynchronous Operating Modes The transmit and receive sections of the ESSI interface are synchronous or asynchronous. The transmitter and receiver use common clock and synchronization signals in Synchronous mode; they use separate clock and sync signals in Asynchronous mode. ...
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Operating Modes: Normal, Network, and On-Demand 7.4.5 Frame Sync Length for Multiple Devices The ability to mix frame sync lengths is useful to configure systems in which data is received from one type of device (for example, codec) and transmitted ...
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Byte Format (LSB/MSB) for the Transmitter Some devices, such as CODECs, require a MSB-first data format. Other devices, such as those that use the AES–EBU digital audio format, require the LSB first compatible with all formats, the ...
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ESSI Programming Model 7.5 ESSI Programming Model The ESSI is composed of the following registers: n Two control registers (CRA, CRB), page 7-14 and page 7-18 n One status register (SSISR), page 7-28 n One Receive Shift Register, page 7-29 ...
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Table 7-3. ESSI Control Register A (CRA) Bit Definitions Bit Number Bit Name Reset Value SSC1 0 21–19 WL[2–0] 0 Enhanced Synchronous Serial Interface (ESSI) Description Reserved. Write to 0 for future compatibility. Select SC1 Controls the ...
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ESSI Programming Model Table 7-3. ESSI Control Register A (CRA) Bit Definitions (Continued) Bit Number Bit Name Reset Value 18 ALC 0 17 16–12 DC[4– PSR 0 10–8 0 7–0 PM[7–0] 0 7-16 Description Alignment Control The ESSI ...
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Flag0 Out CRB(TE1) CRB(OF0) (Sync Mode) CRB(SYN) = SCn0 Sync SYN = 0 Flag0 Async: CRB(SCD0) RX clk SCKn Sync: TX/RX clk Async: CRB(SCKD) TX clk CRA(PSR (Opposite ...
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ESSI Programming Model 7.5.2 ESSI Control Register B (CRB) CRB is one of two read/write control registers that direct the operation of the ESSI (see Figure 7-5). The CRB bit definitions are presented in Table 7-4. CRB controls the ESSI ...
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Enable (TEIE) bits. In Network mode, if you clear the appropriate TE bit and set it again, then you disable the corresponding transmitter ( after transmission of the current data word. The transmitter remains disabled until the ...
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ESSI Programming Model Table 7-4. ESSI Control Register B (CRB) Bit Definitions (Continued) Bit Number Bit Name Reset Value 18 TIE TE0 7-20 0 Transmit Interrupt Enable Enables/disables a DSP transmit interrupt; the interrupt is generated when ...
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Table 7-4. ESSI Control Register B (CRB) Bit Definitions (Continued) Bit Number Bit Name Reset Value 15 TE1 0 14 TE2 0 13 MOD 0 12 SYN 0 Enhanced Synchronous Serial Interface (ESSI) Description Transmit 1 Enable Enables the transfer ...
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ESSI Programming Model Table 7-4. ESSI Control Register B (CRB) Bit Definitions (Continued) Bit Number Bit Name Reset Value 11 CKP 10 FSP 9 FSR 8–7 FSL[1–0] 6 SHFD 5 SCKD 7-22 0 Clock Polarity Controls which bit clock edge ...
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Table 7-4. ESSI Control Register B (CRB) Bit Definitions (Continued) Bit Number Bit Name Reset Value 4 SCD2 0 3 SCD1 0 2 SCD0 0 1 OF1 0 0 OF0 0 Enhanced Synchronous Serial Interface (ESSI) Description Serial Control Direction ...
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ESSI Programming Model Serial Clock RX, TX Frame SYNC RX, TX Serial Data NOTE: Frame sync occurs while data is valid. Serial Clock RX, TX Frame SYNC RX, TX Serial Data NOTE: Frame sync occurs for one bit time preceding ...
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External Transmit Clock SCK Internal Clock ESSI Bit Clock External Receive Clock SC0 NOTE: Transmitter and receiver may have different clocks and frame syncs. External Clock SCK Internal Clock ESSI Bit Clock NOTE: Transmitter and receiver may have the same ...
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Serial Clock Frame SYNC Transmitter Interrupt (or DMA Request) and Serial Data Data NOTE: Interrupts occur and data is transferred once per frame sync. Serial Clock Frame SYNC Transmitter Interrupts (or DMA Request) and Slot 1 Serial Data NOTE: Interrupts ...
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Frame SYNC (FSL0 = 0, FSL1 = 0) Frame SYNC (FSL0 = 0, FSL1 = 1) Data Out Flags Figure 7-9. Normal Mode, External Frame Sync (8 Bit, 1 Word in Frame) Frame SYNC (FSL0 = 0, FSL1 = 0) ...
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ESSI Programming Model 7.5.3 ESSI Status Register (SSISR) The SSISR is a read-only status register by which the DSP reads the ESSI status and serial input flags —Reserved bit; read as 0; ...
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Table 7-5. ESSI Status Register (SSISR) Bit Definitions (Continued) Bit Number Bit Name Reset Value 3 RFS 2 TFS 1 IF1 0 IF0 7.5.4 ESSI Receive Shift Register The 24-bit Receive Shift Register (see Figure 7-12 and Figure 7-13) receives ...
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ESSI Programming Model 7.5.5 ESSI Receive Data Register (RX) The Receive Data Register (RX 24-bit read-only register that accepts data from the receive shift register as it becomes full, according to Figure 7-12 and Figure 7-13. The data ...
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Receive High Byte Serial Receive Receive High Byte Shift Register MSB LSB 8-bit Data MSB 12-bit Data MSB 16-bit Data MSB (a) Receive Registers Transmit ...
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ESSI Programming Model Receive High Byte Receive High Byte SR 7 MSB LSB 8-bit Data MSB 12-bit Data MSB 16-bit Data MSB (a) Receive Registers Transmit High Byte 7 0 ...
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ESSI Transmit Data Registers (TX[2–0]) ESSI0:TX20, TX10, TX00; ESSI1:TX21, TX11, TX01 TX2, TX1, and TX0 are 24-bit write-only registers. Data written into these registers automatically transfers to the transmit shift registers. (See Figure 7-12 and Figure 7-13.) The data ...
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ESSI Programming Model TS27 TS26 TS25 TS24 —Reserved bit; read as 0; write for future compatibility. (ESSI0 X:$FFFFB3, ESSI1 X:$FFFFA3) Figure 7-15. ESSI Transmit Slot Mask Register B (TSMB) ...
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Receive Slot Mask Registers (RSMA, RSMB) Both receive slot mask registers are read/write registers. In Network mode, the receiver(s) use these registers to determine which action to take in the current time slot. Depending on the setting of the ...
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GPIO Signals and Registers 7.6 GPIO Signals and Registers The functionality of each ESSI port is controlled by three registers: port control register (PCRC, PCRD), port direction register (PRRC, PRRD), and port data register (PDRC, PDRD). 7.6.1 Port Control Registers ...
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Port Direction Registers (PRRC and PRRD) The read/write PRRC and PRRD control the data direction of the ESSI0 and ESSI1 GPIO signals when they are enabled by the associated Port Control Register (PCRC or PCRD, respectively). When PRRC[i] or ...
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GPIO Signals and Registers 7.6.3 Port Data Registers (PDRC and PDRD) Bits 5–0 of the read/write PDRs write data to or read data from the associated ESSI GPIO signal lines if they are configured as GPIO signals port ...
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Chapter 8 Serial Communication Interface (SCI) The DSP56L307 Serial Communication Interface (SCI) provides a full-duplex port for serial communication with other DSPs, microprocessors, or peripherals such as modems. The SCI interfaces without additional logic to peripherals that use TTL-level signals. ...
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Operating Modes These modes are selected by the SCR WD[2–0] bits. Synchronous data mode is essentially a high-speed shift register for I/O expansion and stream-mode channel interfaces. A gated transmit and receive clock compatible with the Intel 8051 serial interface ...