C8051F800-TB Silicon Laboratories Inc, C8051F800-TB Datasheet - Page 14

• Manufacturer Part Number: C8051F800-TB
• Description: BOARD EVAL C8051F800
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F800-TB

• Contents: Board
• Processor To Be Evaluated: C8051F800-GM
• Processor Series: C8051F8xx
• Interface Type: USB
• Operating Supply Voltage: 1.8 V to 3.6 V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F8xx
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1796

C8051F800-DK
7.8. Analog I/O, Voltage and Ground Reference Options (TB1, J5, J10)
Several of the C8051F800 target device’s port pins are connected to the TB1 terminal block. Refer to Table 4 for
the TB1 terminal block connections. The J5 header connects the MCU VREF pin (P0.0) to the VREF bypass
capacitors C18 and C19, and also to TB1 pin 6 for an optional external VREF input. The J10 header connects P0.1
to GND, and is useful if the P0.1/AGND option is enabled via the REF0CN register in the C8051F800. Refer to the
C8051F80x-83x data sheet for more information on configuring the voltage and ground reference options.
7.9. C2 Pin Sharing
On the C8051F800, the debug pins C2CK and C2D are shared with the pins RST and P2.0 respectively. The target
board includes the resistors necessary to enable pin sharing which allow the RST and P2.0 pins to be used
normally while simultaneously debugging the device. See Application Note “AN124: Pin Sharing Techniques for the
C2 Interface” at
14
www.silabs.com
Table 4. TB1 Terminal Block Pin Descriptions
for more information regarding pin sharing.
Pin #
1
2
3
4
5
6
P0.0/VREF (Voltage Reference)
Rev. 0.1
P0.6/CNVSTR
GND (Ground)
Description
P0.1/AGND
P1.0
P1.1