C8051F226-TB Silicon Laboratories Inc, C8051F226-TB Datasheet - Page 77

• Manufacturer Part Number: C8051F226-TB
• Description: BOARD PROTOTYPING W/C8051F226
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F226-TB

• Contents: Board
• Processor To Be Evaluated: C8051F22x and C8051F23x
• Interface Type: USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F226
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9.4.6. Interrupt Register Descriptions
The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to
the datasheet section associated with a particular on-chip peripheral for information regarding valid inter-
rupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
0: Disable all Timer 0 interrupts.
Bit0:
R/W
Bit7
EA
EA: Enable All Interrupts.
This bit globally enables/disables all interrupts. It overrides the individual interrupt mask set-
tings.
0: Disable all interrupt sources.
1: Enable each interrupt according to its individual mask setting.
UNUSED. Read = 0, Write = don't care.
ET2: Enable Timer 2 Interrupt.
This bit sets the masking of the Timer 2 interrupt.
0: Disable all Timer 2 interrupts.
1: Enable interrupt requests generated by the TF2 flag (T2CON.7)
ES: Enable Serial Port (UART) Interrupt.
This bit sets the masking of the Serial Port (UART) interrupt.
0: Disable all UART interrupts.
1: Enable interrupt requests generated by the R1 flag (SCON.0) or T1 flag (SCON.1).
ET1: Enable Timer 1 Interrupt.
This bit sets the masking of the Timer 1 interrupt.
0: Disable all Timer 1 interrupts.
1: Enable interrupt requests generated by the TF1 flag (TCON.7).
EX1: Enable External Interrupt 1.
This bit sets the masking of external interrupt 1.
0: Disable external interrupt 1.
1: Enable interrupt requests generated by the /INT1 pin.
ET0: Enable Timer 0 Interrupt.
This bit sets the masking of the Timer 0 interrupt.
1: Enable interrupt requests generated by the TF0 flag (TCON.5).
EX0: Enable External Interrupt 0.
This bit sets the masking of external interrupt 0.
0: Disable external interrupt 0.
1: Enable interrupt requests generated by the /INT0 pin.
R/W
Bit6
-
ET2
R/W
Bit5
SFR Definition 9.8. IE: Interrupt Enable
R/W
ES
Bit4
ET1
R/W
Bit3
Rev. 1.6
EX1
R/W
Bit2
ET0
R/W
Bit1
(bit addressable)
C8051F2xx
EX0
R/W
Bit0
SFR Address:
Reset Value
00000000
0xA8
77