C8051F700DK Silicon Laboratories Inc, C8051F700DK Datasheet - Page 12

• Manufacturer Part Number: C8051F700DK
• Description: DEV KIT FOR C8051F700
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F700DK

• Contents: Board, Cables, CD, Debugger, Power Supply
• Processor To Be Evaluated: C8051F7x
• Processor Series: C8051F7xx
• Interface Type: USB
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F7xx
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1635

C8051F700-DK
6.5. Target Board DEBUG Interface (DEBUG / P3)
The DEBUG connector J9 provides access to the DEBUG (C2) pins of the C8051F700. It is used to connect the
Serial Adapter or the USB Debug Adapter to the target board for in-circuit debugging and Flash programming.
Table 2 shows the DEBUG pin definitions.
6.6. Port I/O Connectors (J0-J6)
Each of the parallel ports of the C8051F700 has its own 10-pin header connector. Each connector provides a pin
for the corresponding port pins 0-7, VDD, and digital ground. The same pin-out is used for all of the port
connectors, and is shown in Table 3 .
6.7. Serial Interface (P4)
A USB-to-UART bridge circuit (U2) and USB connector (P4) are provided on the target board to facilitate serial
connections to UART0 of the C8051F700. The Silicon Labs CP2103 USB-to-UART bridge provides data
connectivity between the C8051F700 and the PC via a USB port. The TX and RX signals of UART0 may be
connected to the CP2102 by installing shorting blocks on header J17. The shorting block between VDD and VIO on
header J12[1-2] is required when using this interface. Optionally, firmware can use I/O pins for hardware
handshaking (/RTS and /CTS). The shorting block positions for connecting each of these signals to the CP2103
are listed in Table 4. To use this interface, the USB-to-UART device drivers should be installed as described in
Section "4.1. CP210x USB to UART VCP Driver Installation" on page 3.
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Table 3. Port I/O Connector Pin Description
Table 2. Debug Connector (P3) Description
2, 3, 9
Pin #
Pin #
10
1
4
5
6
7
8
10
1
2
3
4
5
6
7
8
9
Rev. 0.2
VDD_F700 (+3.3 VDC)
USB Power (+5 VDC)
VDD (VDD_F700)
Pin Description
GND (Ground)
GND (Ground)
Not connected
Not connected
/RST (Reset)
Description
/RST/C2CK
Pn.0
Pn.1
Pn.2
Pn.3
Pn.4
Pn.5
Pn.6
Pn.7
C2D