Z8F04A28100KITG Zilog, Z8F04A28100KITG Datasheet - Page 14

• Manufacturer Part Number: Z8F04A28100KITG
• Description: KIT DEV Z8 ENCORE XP 28-PIN
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F04A28100KITG

• Contents: Hardware, Software and Documentation
• Processor To Be Evaluated: Z8 Family
• Processor Series: Z8 Encore XP
• Interface Type: RS-232, USB, Serial
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.7 V to 3.6 V
• Silicon Manufacturer: Zilog
• Core Architecture: Z8 Encore
• Silicon Core Number: Z8F042ASJ020
• Silicon Family Name: XP F042A
• Rohs Compliant: Yes
• For Use With/related Products: Z8 Encore! XP 28-pin
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4629

Schematics
D
C
B
A
VCC_33V
TABLE 2
Internal Only
Crystal
Ceramic Res
External CMOS
(Use PA0_T0IN
pin on JP2)
R20
R20
0
0
Clock Mode
GND
NOTE 3:
Resistors R20 and R21 are not populated. See Note 2.
PA6_nT1OUT
PA7_T1OUT
PC3_COUT
C19
C19
R21
R21
0
0
R14
R14
0
0
PA0_T0IN_JP
PA1_T0OUT_JP
1
PA3_CTS0
PA4_RXD0
PB1_ANA1
PB2_ANA2
PB3_ANA3
VCC_33V
PA0_T0IN
PA1_T0OUT
GND
PA2
Y1
Y1
1
VCC_33V
GND
1
1
1
D2
D2
GREEN
GREEN
D3
D3
YELL
YELL
D4
D4
RED
RED
20 MHz
20 MHz
0 Ohm
0 Ohm
none
R14
1M
1M
none
R18
R18
3
10
1
2
3
4
5
6
7
8
9
3
5
5
2
2
2
Z8F04xA
Z8F04xA
U6
U6
PB1/ANA1
PB2/ANA2
PB3/CLKIN/ANA3
VDD
PA0/T0IN/T0OUT/XIN/
PA1/T0OUT/XOUT
GND
PA2/DE
PA3/CTS0
PA4/RXD0
R15
none
0 Ohm
none
0 Ohm
C20
C20
R15
R15
0
0
NOTE 2
R7
R7
R8
R8
R10
R10
20 pin footprint
100
100
10
10
none
none
R18
none
none
100
100
Figure 3. Schematic, Z8 Encore! XP F042A Series MCU Development Board, Page 1 of 2
Yes
none
C19
none
PC0/ANA4/CINP/LED
PC1ANA5/CINN/LED
none
PA6/T1IN/T1OUT
PC3/COUT/LED
PC2/ANA6/LED
VCC_33V
RESET/PD0
PA7/T1OUT
PB0/ANA0
PA5/TXD0
none
C20
none
Yes
none
DBG
R9
R9
100K
100K
20
19
18
17
16
15
14
13
12
11
Y1
none
Yes
Yes
none
R11
R11
100
100
PB0_ANA0
PC3_COUT
PC2_ANA6
PC1_ANA5
PC0_ANA4
PA7_T1OUT
PA6_nT1OUT
PA5_TXD0
4
4
VCC_33V
DBG
PD0
Note 2:
clock
support the clock mode selected.
shipped
internal
pins 7 and 8 could be used as GPIO ports PA0 and PA1. To do
so install R20 and R21.
Table 2 shows the recommended clock mode configurations.
GND
ceramic resonator, external R/C and external CMOS drive
PA2
TEST
SW2
SW2
modes.
R16 0
R16 0
PB0_ANA0
1
C23
C23
30uF
30uF
+
+
The XP supports internal, external crystal, external
configured for external 20MHz ceramic resonator or
clock operation. When using Internal oscilator,
GND
U8
U8
IO
R12
R12
NOTE 1:
0
0
C22
C22
0.033uF
0.033uF
R14, R15, R18, C19, C20 and Y1 are used to
EMI Filter
EMI Filter
0.033uF
0.033uF
SENSE
IO
C11
C11
0.001uF
0.001uF
PB1_ANA1
3
C21
C21
R17 0
R17 0
0.001uF
0.001uF
PA3_CTS0
PA4_RXD0
PA5_TXD0
NOTE 1:
C10
C10
Note 1:
PB6 and PB7 are dual function pins (GPIO or Analog
R12, R13, R16, and R17 are zero-ohm resistors used in
conjunction
desired. C21, C22, and C23 are bypass capacitors that are used
for better noise rejection. U8 is an optional filter that can
be used to improve the
development board is shipped configured for
Table 1 shows the configurations
C12
C12
0.001uF
0.001uF
PB2_ANA2
PB2_ANA2
PB4_ANA7
PB3_ANA3
PA0_T0IN
PA1_T0OUT
PB7
PB5
R13
R13
0
0
VCC_33V
PA2
PA3_CTS0
PA4_RXD0
PA5_TXD0
GND
The development board is
C13
C13
0.001uF
0.001uF
PB3_ANA3
3
with GPIO Control Registers to select function
3
PB6
10
11
12
13
14
1
2
3
4
5
6
7
8
9
Analog
Supply
GPIO
U5
U5
PB2/ANA2
PB4/ANA7
PB5/Vref
PB3/ANA3/CLKIN
PB6(AVDD)
VDD
PA0/T0IN/T0OUTXIN
PA1/T0OUT/XOUT
GND
PB7(AGND)
PA2/DE
PA3/CTS0
PA4/RXD0
PA5/TXD0
R22
R22
28 pin footprint
C14
C14
0.001uF
0.001uF
PC0_ANA4
0
0
OUT
R12
IN
Z8F04xA_28
Z8F04xA_28
quality of the Analog Supply. The
OUT
PB5_JP
R13 R16
IN
C15
C15
0.001uF
0.001uF
PC1_ANA5
TABLE 1
OUT
IN
PC1/ANA5/CINN/LED
PC0/ANA4/CINP/LED
recommended
PA6/T1IN/T1OUT
PC3/COUT/LED
GND
PC2/ANA6/LED
PB0_ANA0
PB1_ANA1
PB2_ANA2
PB3_ANA3
PC0_ANA4
PC1_ANA5
PC2_ANA6
PB4_ANA7
OUT
IN
RESET/PD0
R17
PA7/T1OUT
PB1/ANA1
PB0/ANA0
PC7/LED
PC6/LED
PC5/LED
PC4/LED
C16
C16
0.001uF
0.001uF
RESET/TEST2
PC2_ANA6
Z8 Encore! XP
DBG
SW1
SW1
IN
R22
OUT
Analog Supply.
11
13
15
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
3
5
7
9
JP5
JP5
HEADER 2
HEADER 2
J2
J2
HEADER 8X2
HEADER 8X2
U8
OUT
1
2
C17
C17
0.001uF
0.001uF
optional
PB1_ANA1
PB0_ANA0
PC3_COUT
PC2_ANA6
PC1_ANA5
PC0_ANA4
PA6_nT1OUT
PB4_ANA7
supply)
DBG
PD0
PC7
PC6
PA7_T1OUT
PC5
PC4
2
4
6
8
10
12
14
16
2
2
C21...C23
C18
C18
0.001uF
0.001uF
GND
OUT
IN
R19 10K
R19 10K
DBG
®
Title
Title
Title
Size
Size
Size
Date:
Date:
Date:
B
B
B
F042A Series Development Kit
If Module is plugged onto the Dev Platform the local
RS232 interface is disabled by pin 50 of JP2
XP 4K MDS Processor Module. Schematic.
XP 4K MDS Processor Module. Schematic.
XP 4K MDS Processor Module. Schematic.
Document Number
Document Number
Document Number
PB4_ANA7
PC1_ANA5
PB3_ANA3
PB1_ANA1
VCC_33V
PC4
PC7
PC3_COUT
PA6_nT1OUT
PA7_T1OUT
PA3_CTS0
PA4_RXD0
PB6
PB7
-RESET
Tuesday, March 18, 2008
Tuesday, March 18, 2008
Tuesday, March 18, 2008
GND
GND
VCC_33V
VCC_33V
GND
GND
-TRSTN
-CS2
GND
A21
A22
-CS0
-BUSACK
-F91_WE
A6
A10
A8
A13
A15
A18
A19
A2
A11
A4
A5
D1
D3
D5
D7
-MREQ
-WR
96C0941-001
96C0941-001
96C0941-001
connector 1
for
reference
only
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
1
3
5
7
9
JP2
JP2
HEADER 30x2/SM
HEADER 30x2/SM
HEADER 30x2/SM
HEADER 30x2/SM
JP1
JP1
connector 2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
Sheet
Sheet
Sheet
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
1
1
UM016608-0608
-DIS_IrDA
PC2_ANA6
PC0_ANA4
PB2_ANA2
PB0_ANA0
VCC_33V
VCC_33V
-DIS_FLASH
VCC_33V
A0
A3
A14
A16
A23
-CS1
GND
User Manual
A7
A9
A17
D0
D2
D4
D6
-IOREQ
-RD
-INSTRD
-BUSREQ
GND
PC5
PC6
PA0_T0IN_JP
PA1_T0OUT_JP
PA5_TXD0
GND
A1
A12
A20
2
2
2
PB5_JP
PA2
PD0
GND
GND
GND
of
of
of
-DIS_232
-DIS_IRDA
3
3
3
Rev
Rev
Rev
D
D
D
D
C
B
A
10