DK-START-4CGX15N Altera, DK-START-4CGX15N Datasheet - Page 24

• Manufacturer Part Number: DK-START-4CGX15N
• Description: KIT STARTER CYCLONE IV GX
• Manufacturer: Altera
• Series: Cyclone® IVr
• Type: FPGAr

Specifications of DK-START-4CGX15N

• Contents: Board, Cables, Power Supply
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone
• Silicon Core Number: EP4C
• Silicon Family Name: Cyclone IV GX
• Kit Contents: Board, Cables, PSU, CD
• Rohs Compliant: Yes
• For Use With/related Products: Cyclone IV GX
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2569

6–6
The GPIO Tab
Cyclone IV GX Transceiver Starter Kit User Guide
1
1
■
■
■
■
Because the Config tab requires that a specific design is running in the FPGA, writing
a 0 to SRST or changing the PSO value can cause the Board Test System to stop
running.
JTAG Chain
The JTAG chain devices control shows all the devices currently in the JTAG chain.
The Cyclone IV GX device is always the first device in the chain.
Setting DIP switch S8.3 to the off position includes the MAX II device in the JTAG
chain.
Flash Memory Map
The Flash memory map control shows the memory map of the flash memory device
on your board.
The GPIO tab allows you to interact with all the general purpose user I/O
components on your board. You can write to the LCD, turn LEDs on or off, and detect
push button presses.
PSO—Sets the MAX II PSO register. The following options are available:
■
■
PSR—Sets the MAX II PSR register. The numerical values in the list corresponds to
the page of flash memory to load during FPGA reconfiguration. Refer to
for more information.
PSS—Displays the MAX II PSS register value. Refer to
available options.
SRST—Resets the system and reloads the FPGA with a design from flash memory
based on the other MAX II register values. Refer to
Use PSR—Allows the PSR to determine the page of flash memory to use for
FPGA reconfiguration.
Use PSS—Allows the PSS to determine the page of flash memory to use for
FPGA reconfiguration.
Figure 6–3
shows the GPIO tab.
Table 6–2
Table 6–2
© March 2010 Altera Corporation
Chapter 6: Board Test System
for more information.
Using the Board Test System
for the list of
Table 6–2