AT91SAM9260-EK Atmel, AT91SAM9260-EK Datasheet - Page 11

• Manufacturer Part Number: AT91SAM9260-EK
• Description: KIT EVAL FOR AT91SAM9260
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9260-EK

• Contents: Evaluation Board, Parallel Cable and CD-ROM
• Processor To Be Evaluated: AT91SAM9260
• Data Bus Width: 32 bit
• Interface Type: RS-232, Ethernet, USB
• Core: ARM 9
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: ARM926EJ-S
• Silicon Core Number: AT91SAM9260
• Silicon Family Name: ARM
• Kit Contents: Board, Cables, CD, Power Supply
• Rohs Compliant: Yes
• For Use With/related Products: AT91SAM9260
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.1
AT91SAM9260-EK Evaluation Board User Guide
AT91SAM9260
Microcontroller
• Incorporates the ARM926EJ-S™ ARM
• Additional Embedded Memories
• External Bus Interface (EBI)
• USB 2.0 Full Speed (12 Mbits per second) Device Port
• USB 2.0 Full Speed (12 Mbits per second) Host Single Port in the 208-lead PQFP
• Ethernet MAC 10/100 Base T
• Image Sensor Interface
• Bus Matrix
• Fully-featured System Controller, including
• Reset Controller (RSTC)
Package and Double Port in 217-ball LFBGA Package
– DSP Instruction Extensions, ARM Jazelle
– 8-KByte Data Cache, 8-KByte Instruction Cache, Write Buffer
– 200 MIPS at 180 MHz
– Memory Management Unit
– EmbeddedICE
– One 32-KByte Internal ROM, Single-cycle Access At Maximum Matrix Speed
– Two 4-KByte Internal SRAM, Single-cycle Access At Maximum Matrix Speed
– Supports SDRAM, Static Memory, ECC-enabled NANDFlash and CompactFlash
– On-chip Transceiver, 2,432-byte Configurable Integrated DPRAM
– Single or Dual On-chip Transceivers
– Integrated FIFOs and Dedicated DMA Channels
– Media Independant Interface or Reduced Media Independant Interface
– 28-byte FIFOs and Dedicated DMA Channels for Receive and Transmit
– ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate
– 12-bit Data Interface for Support of High Sensibility Sensors
– SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format
– Six 32-bit-layer Matrix
– Boot Mode Select Option, Remap Command
– Reset Controller, Shutdown Controller
– Four 32-bit Battery Backup Registers for a Total of 16 Bytes
– Clock Generator and Power Management Controller
– Advanced Interrupt Controller and Debug Unit
– Periodic Interval Timer, Watchdog Timer and Real-time Timer
– Based on a Power-on Reset Cell, Reset Source Identification and Reset Output
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, Debug Communication Channel Support
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Thumb
Board Description
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Technology for Java
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Processor
Section 3
6234C–ATARM–22-Mar-07
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Acceleration
3-1
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