ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 9
![KIT DEV/EVAL FOR AVR32 AT32UC3A](/photos/9/20/92035/atevk1104_sml.jpg)
ATEVK1104
Manufacturer Part Number
ATEVK1104
Description
KIT DEV/EVAL FOR AVR32 AT32UC3A
Manufacturer
Atmel
Series
AVR®32r
Type
MCUr
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.ATEVK1104.pdf
(826 pages)
3.ATEVK1104.pdf
(90 pages)
4.ATEVK1104.pdf
(6 pages)
5.ATEVK1104.pdf
(12 pages)
Specifications of ATEVK1104
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT32UC3A3
Data Bus Width
32 bit
Interface Type
USB, SPI, USART
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
AVR UC3
Silicon Core Number
AT32UC3A3256
Silicon Family Name
AVR
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT32UC3A3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATEVK1104
Manufacturer:
Atmel
Quantity:
135
Peripheral DMA Controller
The Atmel Peripheral DMA controller sets a
new standard for data transfer efficiency. If
the Peripheral DMA controller is not en-
abled, the maximum usable transfer rate on
the SPI module would be approximately 1
MBit/s, occupying the CPU with more than
50% load just moving data around. With the
Peripheral DMA controller this bottleneck is
removed and the AVR32 UC3 microcontroller
can achieve a transfer rate of 33 MBit/s on
SPI and USART with only a 15% load on the
CPU. The UC3 can even toggle the I/O pins
at 33 MHz.
A higher level interrupt will halt execution of a lower level interrupt routine. The lower level
interrupt routine will continue and finish after the higher level interrupt routine finishes.
A second interrupt at an interrupt level already being serviced, will pend until the first
interrupt routine finishes.
Interrupt Controller
The 32-bit AVR UC3 CPU includes a multi-level interrupt
controller. Four priority levels are supported where higher
level interrupts are prioritized and executed before low level
interrupts. All peripherals can be assigned any interrupt level
and the interrupt vector addresses can be changed without
stopping the CPU. Interrupt latencies are very fast, typically
11 clock cycles including saving the register file to the stack.
Medium-level
Medium-level
Medium-level
High-level
High-level
Low-level
Main
Main
Program Flow and Interrupt execution
Program Flow and Interrupt execution
1
1
1
2
2
1
1
HOLD
3
3
HOLD
HOLD
HOLD
www.atmel.com
3
3
2
2
1
1
Main
Main
2
2
1
1
Main
Main
page 8