LM95235EVAL/NOPB National Semiconductor, LM95235EVAL/NOPB Datasheet - Page 24

• Manufacturer Part Number: LM95235EVAL/NOPB
• Description: BOARD EVALUATION LM95235
• Manufacturer: National Semiconductor
• Series: PowerWise®, TruTherm®r

Specifications of LM95235EVAL/NOPB

• Sensor Type: Temperature
• Sensing Range: -40°C ~ 125°C
• Interface: SMBus (2-Wire/I²C)
• Sensitivity: ±1°C
• Voltage - Supply: 3 V ~ 3.6 V
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: LM95235
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LM95235EVAL

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3.1.3 Compensating for Different Non-Ideality
In order to compensate for the errors introduced by non-ide-
ality, the temperature sensor is calibrated for a particular
processor. National Semiconductor temperature sensors are
always calibrated to the typical non-ideality and series resis-
tance of a given processor type. The LM95235 is calibrated
for two non-ideality factors and series resistance values thus
supporting the MMBT3904 transistor and Intel processors on
65nm process without the requirement for additional trims.
For most accurate measurements TruTherm mode should be
turned on when measuring the Intel processor on 65nm pro-
cess to minimize the error introduced by the false non-ideality
spread (see 3.1.1 Diode Non-Ideality Factor Effect on Accu-
racy). When a temperature sensor calibrated for a particular
processor type is used with a different processor type, addi-
tional errors are introduced.
Temperature errors associated with non-ideality of different
processor types may be reduced in a specific temperature
range of concern through use of software calibration. Typical
Non-ideality specification differences cause a gain variation
of the transfer function, therefore the center of the tempera-
ture range of interest should be the target temperature for
calibration purposes. The following equation can be used to
calculate the temperature correction factor (T
compensate for a target non-ideality differing from that sup-
ported by the LM95235.
where
•
•
•
The correction factor should be directly added to the temper-
ature reading produced by the LM95235. For example when
using the LM95235, with the 3904 mode selected, to measure
a AMD Athlon processor, with a typical non-ideality of 1.008,
for a temperature range of 60 °C to 100 °C the correction fac-
tor would calculate to:
Therefore, 1.75°C should be subtracted from the temperature
readings of the LM95235 to compensate for the differing typ-
ical non-ideality target.
Pentium M
(Centrino)
MMBT3904
AMD Athlon MP
model 6
AMD Athlon 64
AMD Opteron
AMD Sempron
η
η
T
S
PROCESSOR
CR
= LM95235 non-ideality for accuracy specification
= center of the temperature range of interest in °C
= Processor thermal diode typical non-ideality
1.00151 1.00220 1.00289
1.002
1.008
1.008
1.00261
1.003
1.008
1.008
1.008
1.016
1.096
1.096
CF
) required to
3.06
0.93
(7)
(8)
24
3.2 PCB LAYOUT FOR MINIMIZING NOISE
In a noisy environment, such as a processor mother board,
layout considerations are very critical. Noise induced on
traces running between the remote temperature diode sensor
and the LM95235 can cause temperature conversion errors.
Keep in mind that the signal level the LM95235 is trying to
measure is in microvolts. The following guidelines should be
followed:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Noise coupling into the digital lines greater than 400 mVp-p
(typical hysteresis) and undershoot less than 500 mV below
GND, may prevent successful SMBus communication with
the LM95235. SMBus no acknowledge is the most common
symptom, causing unnecessary traffic on the bus. Although
V
parallel with 100 pF. The 100 pF capacitor should be
placed as close as possible to the power supply pin. A
bulk capacitance of approximately 10 µF needs to be in
the near vicinity of the LM95235.
A 100 pF diode bypass capacitor is recommended to filter
high frequency noise but may not be necessary. Make
sure the traces to the 100 pF capacitor are matched.
Place the filter capacitors close to the LM95235 pins.
Ideally, the LM95235 should be placed within 10 cm of
the Processor diode pins with the traces being as
straight, short and identical as possible. Trace resistance
of 1Ω can cause as much as 0.62°C of error. This error
can be compensated by using simple software offset
compensation.
Diode traces should be surrounded by a GND guard ring
to either side, above and below if possible. This GND
guard should not be between the D+ and D− lines. In the
event that noise does couple to the diode lines it would
be ideal if it is coupled common mode. That is equally to
the D+ and D− lines.
Avoid routing diode traces in close proximity to power
supply switching or filtering inductors.
Avoid running diode traces close to or parallel to high
speed digital and bus lines. Diode traces should be kept
at least 2 cm apart from the high speed digital traces.
If it is necessary to cross high speed digital traces, the
diode traces and the high speed digital traces should
cross at a 90 degree angle.
The ideal place to connect the LM95235's GND pin is as
close as possible to the Processors GND associated with
the sense diode.
Leakage current between D+ and GND and between D+
and D− should be kept to a minimum. Thirteen nano-
amperes of leakage can cause as much as 0.2°C of error
in the diode temperature reading. Keeping the printed
circuit board as clean as possible will minimize leakage
current.
DD
should be bypassed with a 0.1 µF capacitor in
FIGURE 8. Ideal Diode Trace Layout
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