CY3218-CAPEXP1 Cypress Semiconductor Corp, CY3218-CAPEXP1 Datasheet - Page 36

• Manufacturer Part Number: CY3218-CAPEXP1
• Description: KIT CAPSENSE EXPRESS CY8C20110
• Manufacturer: Cypress Semiconductor Corp
• Series: CapSense Express™r

Specifications of CY3218-CAPEXP1

• Sensor Type: Touch, Capacitive
• Interface: I²C, USB
• Voltage - Supply: 0.9 V ~ 1.5 V
• Embedded: Yes, Other
• Utilized Ic / Part: CY8C20110
• Processor To Be Evaluated: CY8C201x
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Sensitivity: -
• Sensing Range: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2043

Glossary
Document Number: 001-54606 Rev. *E
port
Power on reset
(POR)
PSoC
PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology.
pulse width
modulator (PWM)
RAM
register
reset
ROM
serial
settling time
shift register
slave device
SRAM
SROM
stop bit
synchronous
®
(continued)
A group of pins, usually eight.
A circuit that forces the PSoC device to reset when the voltage is lower than a pre-set level. This is a type of
hardware reset.
Cypress Semiconductor’s PSoC
Chip™ is a trademark of Cypress.
An output in the form of duty cycle which varies as a function of the applied measurand
An acronym for random access memory. A data-storage device from which data can be read out
and new data can be written in.
A storage device with a specific capacity, such as a bit or byte.
A means of bringing a system back to a know state. See hardware reset and software reset.
An acronym for read only memory. A data-storage device from which data can be read out, but
new data cannot be written in.
The time it takes for an output signal or value to stabilize after the input has changed from one
value to another.
A memory storage device that sequentially shifts a word either left or right to output a stream of
serial data.
A device that allows another device to control the timing for data exchanges between two
devices. Or when devices are cascaded in width, the slave device is the one that allows another
device to control the timing of data exchanges between the cascaded devices and an external
interface. The controlling device is called the master device.
An acronym for static random access memory. A memory device where you can store and
retrieve data at a high rate of speed. The term static is used because, after a value is loaded into an SRAM cell,
it remains unchanged until it is explicitly altered or until power is removed from the device.
An acronym for supervisory read only memory. The SROM holds code that is used to boot the
device, calibrate circuitry, and perform Flash operations. The functions of the SROM may be
accessed in normal user code, operating from Flash.
A signal following a character or block that prepares the receiving device to receive the next
character or block.
1. Pertaining to a process in which all events occur one after the other.
2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or
1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal.
2. A system whose operation is synchronized by a clock signal.
channel.
®
is a registered trademark and Programmable System-on-
CY8C20160, CY8C20140
CY8C20110, CY8C20180
CY8C20142
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