MAX9939EVKIT+ Maxim Integrated Products, MAX9939EVKIT+ Datasheet - Page 9

• Manufacturer Part Number: MAX9939EVKIT+
• Description: KIT EVAL FOR MAX9939
• Manufacturer: Maxim Integrated Products

Specifications of MAX9939EVKIT+

• Channels Per Ic: 2 - Dual
• Amplifier Type: Programmable Gain
• Output Type: Differential
• Slew Rate: 9 V/µs
• Current - Output / Channel: 70mA
• Operating Temperature: -40°C ~ 125°C
• Current - Supply (main Ic): 3.4mA
• Voltage - Supply, Single/dual (±): 2.9 V ~ 5.5 V
• Board Type: Fully Populated
• Utilized Ic / Part: MAX9939
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• -3db Bandwidth: -

SHDN: Set SHDN to 0 for normal operation. Set SHDN
to 1 to place the device in a low-power 13µA shutdown
mode. In shutdown mode, the outputs OUTA and OUTB
are high impedance, however, the SPI decode circuitry
is still active. Each instruction requires a write to the
SHDN bit.
MEAS: The MAX9939 provides a means for measuring
its own input offset voltage. When MEAS is set to 1, the
INA- input is disconnected from the input signal path
and internally shorted to INA+. This architecture thus
allows the input common-mode voltage to be compen-
sated at the application-specific input common-mode
voltage of interest. The input offset voltage of the PGA
is the output offset voltage divided by the programmed
gain without any V
Program V
also includes the effect of mismatches in the resistor-
dividers. Setting MEAS to 0 switches the inputs back to
the signals on INA+ and INA-. Each instruction requires
a write to the MEAS bit.
The PGA’s gain is set by the bits G3:G0 in the Gain reg-
ister. Table 3 shows the relationship between the bits
G3:G0 and the amplifier’s gain. The slew rate and
small-signal bandwidth (SSBW) of the PGA depend on
its gain setting as shown in Table 3.
Table 3. Gain
G3:G0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
V
OS-INHERENT
OS
to offset V
0.25 (V
0.2 (V
OS
_______________________________________________________________________________________
with Input V
trim (i.e., V3:V0 set to 0):
GAIN
(V/V)
120
157
CC
CC
10
20
30
40
60
80
= (V
1
1
= 3.3V)
OS-INHERENT
= 5V)
OUTA
- V
SPI Programmable-Gain Amplifier
Programming Gain
CC
SLEW RATE
. The input V
/2)/Gain
(V/µs)
12.80
12.50
13.31
12.15
18.53
16.49
2.90
8.99
8.70
2.86
2.90
OS
OS
Trim and Output Op Amp
The input offset voltage is set by the bits V4:V0 in the
Input Offset Voltage Trim register. Bit V4 determines the
polarity of the offset. Setting V4 to 0 makes the offset
positive, while setting V4 to 1 makes the offset negative.
Table 4 shows the relationship between V3:V0 and V
To determine the effect of V
fier for gains other than 1, use the following formula:
where V
of the amplifier, which can be measured by setting
MEAS to 1.
The output amplifier can be configured as a multiple-
feedback active filter as shown in Figure 3, which tradi-
tionally has better stopband attenuation characteristics
than Sallen-Key filters. These filters also possess inher-
ently better distortion performance since there are no
common-mode induced effects (i.e., the common-
mode voltage of the operational amplifier is always
fixed at V
such as in Sallen-Key filters). Choose external resistors
and capacitors to create lowpass, bandpass, or high-
pass filters.
V
Use of Output Amplifier as Active Filter
OUTA
SMALL-SIGNAL BANDWIDTH (MHz)
OS-INHERENT
CC
= V
Programming Input Offset Voltage (V
/2 instead of it being signal dependent
CC
Applications Information
/2 + Gain x (V
2.15
2.40
1.95
3.40
2.15
2.60
1.91
2.30
1.78
1.95
2.15
is the inherent input offset voltage
OS
at the output of the ampli-
OS-INHERENT
+ V
OS
)
OS
OS
9
)
.