CLC730033 National Semiconductor, CLC730033 Datasheet - Page 3

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CLC730033

Manufacturer Part Number
CLC730033
Description
EVAL BOARD AMP FOR 14-SOIC
Manufacturer
National Semiconductor
Datasheet

Specifications of CLC730033

Channels Per Ic
1 - Single
Amplifier Type
Variable Gain
Board Type
Bare (Unpopulated)
Utilized Ic / Part
LMH6502, LMH6503
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Operating Temperature
-
Output Type
-
Current - Output / Channel
-
Voltage - Supply, Single/dual (±)
-
-3db Bandwidth
-
Slew Rate
-
Current - Supply (main Ic)
-
Other names
*CLC730033
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
BANNED SUBSTANCE COMPLIANCE
National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products
Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification
(CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2.
Nulling the Output DC Offset
output of the device. Figure 5 shows the required external
circuitry necessary to add the appropriate nulling offsets at
both the input buffer and the output amplifier.
The output stage offset should be trimmed prior to the input
stage. With the gain adjust pin set at minimum gain (maxi-
mum attenuation), the output stage offset may be nulled
independently from the input stage. R
to yield the desired output error voltage (typically
Having corrected for the input offset voltage and bias current
errors of the output amplifier, returning the gain adjust pin to
the maximum gain voltage will allow the input buffer stage
DC offset errors to be corrected. With no input signal
present, but with matched source impedances at each of the
two buffer inputs, R
output to within the desired error band.
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(Continued)
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
FIGURE 5. Input and Output Stage DC Nulling
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10
in Figure 5 can be adjusted to bring the
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14
should be adjusted
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<
20093004
1 mV).
2. A critical component is any component of a life
Adjusting the input and the output stage offsets at the two
gain extremes will hold the output DC error at a minimum at
these two points in the gain range. If a more limited gain
range is anticipated, the adjustments should be made at
these operating points. The non-linear DC error introduced
by the multiplier core will cause a residual, gain dependent,
offset to appear at the output as the gain is swept from
minimum to maximum. Also, neither the input nor the output
offset adjustment described here will improve temperature
drift effects.
Printed Circuit Board Layout
The CLC730033 was designed for evaluation of the CLC520
and CLC522 (obsoleted devices, replaced by the LMH6502
and LMH6503).
There is silk-screen on the board referencing CLC520 and
CLC522. Figure 6 shows both component and circuit side
views (gray color depicts the circuit side).
FIGURE 6. CLC730033 (Component and Circuit Side)
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
National Semiconductor
Asia Pacific Customer
Support Center
Email: ap.support@nsc.com
National Semiconductor
Japan Customer Support Center
Fax: 81-3-5639-7507
Email: jpn.feedback@nsc.com
Tel: 81-3-5639-7560
20093006

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