LP3996SD-3030EV National Semiconductor, LP3996SD-3030EV Datasheet

LP3996SD-3030EV

Manufacturer Part Number

LP3996SD-3030EV

Description

BOARD EVALUATION LP3996SD-3030

Manufacturer

National Semiconductor

Datasheets

1.LP3996SD-2828EV.pdf (3 pages)

2.LP3996SD-2828EV.pdf (18 pages)

Specifications of LP3996SD-3030EV

Channels Per Ic

2 - Dual

Voltage - Output

3V, 3V

Current - Output

300mA, 150mA

Voltage - Input

2 ~ 6V

Regulator Type

Positive Fixed

Operating Temperature

-40°C ~ 85°C

Board Type

Fully Populated

Utilized Ic / Part

LP3996

Lead Free Status / RoHS Status

Not applicable / Not applicable

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LP3996 / LP5996

Application Board

Information

General Information

This board is designed to allow the evaluation of either the

LP3996 or the LP5996 Dual Voltage Regulator. Each board

is pre-assembled and tested in the factory. The board con-

tains the LP3996 / LP5996 in a 10 lead LLP package with all

the associated passive components to enable all features of

either device to be tested.

The LP3996 / LP5996 are Dual, Low Drop-out Voltage Regu-

lators with independent enable pins. LDO1 can deliver a

maximum current of 150mA. while LDO2 can deliver up to

300mA. The LP3996 has an ERROR Flag associated with

LDO2. The flag is set to Low if LDO2 is out of regulation and

by adding a capacitor between the SET pin and GND, the

flag may also be used as a delayed Power-On-reset (POR),

see below.

1µF ceramic capacitors are fitted from V

to GND.

The POR feature is not included in the LP5996. Both devices

also have a Bypass pin and by connecting a capacitor (10nF

typ.) to GND, the output noise can be reduced substantially.

Operation

The input voltage, applied between V

at least 0.5V greater than the highest V

than 6.0V. The minimum operating voltage is 2.0V. Loads

can be connected to V

GND. Internal short circuit protection is provided for each

LDO. Additional sense pins, V

vided on the board to allow accurate measurements directly

on the input and output pins of the device, eliminating any

voltage drop on the PCB traces or connecting wires to the

loads. Input leads should be kept reasonably short to mini-

mize inductance. If longer input leads (

may be necessary to increase the value of the input capaci-

tor to 2.2µF to ensure stability.

ON/OFF control is provided by logic signals on EN1 and

EN2. A minimum of 0.95V is required on these pins to enable

the corresponding LDO. The LDOs will be shutdown with the

enable pins set to 0.4V or less. If ON/OFF control is not

required, then either or both enable pins may be connected

to V

EN2 to GND.

. The device has 1MΩ internal resistors from EN1 and

and V

INS

, V

O1S

pins with reference to

and GND, should be

AN201469

1m) are required it

and V

, V

OUT

OUT1

and no more

O2S

and V

are pro-

OUT2

National Semiconductor

Application Note 1377

Morgan Bryce

November 2006

On the LP3996 only, the active low POR flag on LDO2 is

asserted when the output of LDO2 drops below 90% (typical)

of its regulated value indicating that LDO2 is out of regulation

due to an overload or fault condition. During start-up, or

following the removal of a fault condition, the flag will remain

in the Low state until the output of LDO2 reaches 92%

(typical) of its maximum value. By adding, a capacitor be-

tween the SET pin and GND, a delay can be programmed to

the rising state of the POR output which may then be used

as a Power-On-Reset for a micro controller within the user’s

application, for example. The Delay time is set by the follow-

ing formula.

Typically, V

0.1µF capacitor (C2) fitted, the delay time will be around

125ms.

The POR output is an open drain NMOS transistor. It is

pulled up to to V

evaluation board. Note that when the POR is in the HIGH

state, any significant loading, a 1MΩ Oscilloscope input, for

example, will cause the voltage to drop due the 470kΩ

pull-up. A 10X probe should be used. In the LOW state, with

a sink current of 250µA, the POR pin will have a level of

20mV (typical).

Output noise is minimized by the inclusion of a 10nF bypass

capacitor (C5). Together with an internal resistor, this forms a

low-pass filter for the internal reference voltage which re-

duces the noise on both V

The schematic and board layout are shown below:

TH(DELAY)

by a 470kΩ resistor (R1) fitted to the

is 1.25V and I

OUT1

and V

DELAY

20146903

OUT2

is 1µA. So for the

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LP3996SD-3030EV Summary of contents

Page 1

... V . The device has 1MΩ internal resistors from EN1 and IN EN2 to GND. © 2006 National Semiconductor Corporation National Semiconductor Application Note 1377 Morgan Bryce November 2006 On the LP3996 only, the active low POR flag on LDO2 is ...

Page 2

Schematic Diagram PCB Layout Bill of Materials for LP3996 / LP5996 LLP Evaluation Board Item Manufacturer GND) Murata GND) Murata SET GND) Murata OUT1 GND Murata OUT2 ...

Page 3

... National Semiconductor and the National Semiconductor logo are trademarks or registered trademarks of National Semiconductor Corporation. All other brand or product names may be trademarks or registered trademarks of their respective holders. ...

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