LP5952LC-1.5EV National Semiconductor, LP5952LC-1.5EV Datasheet - Page 4

• Manufacturer Part Number: LP5952LC-1.5EV
• Description: BOARD EVALUATION LP5952LC-1.5
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LP5952LC-1.5EV

• Channels Per Ic: 1 - Single
• Voltage - Output: 1.5V
• Current - Output: 350mA
• Voltage - Input: 3 ~ 5.5V
• Regulator Type: Positive Fixed
• Operating Temperature: -40°C ~ 125°C
• Board Type: Fully Populated
• Utilized Ic / Part: LP5952
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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Application Hints
DUAL RAIL SUPPLY
The LP5952 requires two different supply voltages:
•V
voltage
•V
It’s important that V
the device on the evaluation board is used in the typical post
regulation application as shown in FIGURE 1 of the datasheet
using a DC-DC converter to generate V
sequencing of the two power supplies is not an issue as
V
The output voltage of the DC-DC regulator will take some time
to rise up and supply V
always ramp up more slowly than V
In case V
pins will ramp up simultaneously causing no problem.
If the LP5952 evaluation board is used stand alone, two in-
dependent supplies are connected to the LP5952. Therefore
special care must be taken to guarantee that V
≤
POWER DISSIPATION AND DEVICE OPERATION
The permissible power dissipation for any package is a mea-
sure of the capability of the device to pass heat from the power
source, the junctions of the IC, to the ultimate heat sink, the
ambient environment. Thus the power dissipation is depen-
dent on the ambient temperature and the thermal resistance
across the various interfaces between the die and ambient
air.
The allowable power dissipation for the device in a given
package can be calculated using the following equation:
P
With a θ
package returns a value of 1053mW with a maximum junction
temperature of 125°C at T
With a θ
age returns a value of 667mW with a maximum junction
temperature of 125°C at T
The actual power dissipation across the device can be esti-
mated by the following equation:
P
This establishes the relationship between the power dissipa-
tion allowed due to thermal consideration, the voltage drop
across the device, and the continuous current capability of the
device. These two equations should be used to determine the
optimum operating conditions for the device in the application.
As an example for the micro SMD package, to keep full load
BATT
D
D
V
IN
BATT
= (T
≈
BATT
, the power input voltage, is regulated to the fixed output
(V
, the bias input voltage, supplies internal circuitry.
supplies both, the DC-DC regulator and the LP5952.
J(MAX)
IN
.
JA
JA
IN
- V
= 150°C/W, the device in the 6-pin COL LLP pack-
= 95°C/W, the device in the 5 bump micro SMD
is shorted to V
OUT
- T
A
) * I
) / θ
IN
OUT
JA
does not exceed V
IN
of LP5952. In this application V
BATT
A
A
of 25°C or 421mW at T
of 25°C or 267mW at T
, the voltages at the two supply
BATT
.
IN
BATT
out of V
at any time. If
IN
is always
A
A
BATT
of 85°C.
of 85°C.
IN
, the
will
4
current capability of 350mA for a 1.5V output voltage option
at a high ambient temperature of 85°C, V
2.7V:
V
The figure below shows the output current derating due to
these considerations:
The typical contribution of the bias input voltage supply
V
V
EXTERNAL CAPACITORS
If the LP5952 evaluation board is used stand alone (V
V
capacitor at V
pacitor of 1.0µF is recommended and assembled at the power
input pin V
A capacitor at V
supply does not exceed 5cm. Therefore no capacitor is as-
sembled by default, but a footprint is provided on the evalua-
tion board.
At the output (C3) a 2.2µF ceramic capacitor is recommended
and assembled.
For further details on recommended capacitors and capacitor
characteristics please see bill of materials above and the
datasheet.
IN
BATT
BATT
BATT
T
≤
A
P
to the power dissipation can be neglected: P
* I
directly connected to a dual power supply), an input
= 85°C, θ
D
Q_VBATT
/ I
Maximum Load Current vs V
IN
OUT
.
IN
+ V
BATT
JA(MICROSMD)
= 5.5V * 50µA = 0.275mW typical.
(C2) is required for stability. A ceramic ca-
Output Current Derating
OUT
(C1) is not required if the distance to the
= 421mW / 350mA + 1.5V = 2.7V.
= 95°C/W, θ
IN
IN
JA(LLP)
- V
has to be kept
OUT
= 150°C
20210211
,
D_VBATT
IN
and
≤
=