ADP1715-3.3-EVALZ Analog Devices Inc, ADP1715-3.3-EVALZ Datasheet - Page 15

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ADP1715-3.3-EVALZ

Manufacturer Part Number
ADP1715-3.3-EVALZ
Description
BOARD EVAL FOR ADP1715-3.3
Manufacturer
Analog Devices Inc
Datasheet

Specifications of ADP1715-3.3-EVALZ

Channels Per Ic
1 - Single
Voltage - Output
3.3V
Current - Output
500mA
Voltage - Input
2.5 ~ 5.5V
Regulator Type
Positive Fixed
Operating Temperature
-40°C ~ 125°C
Board Type
Fully Populated
Utilized Ic / Part
ADP1715
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
140
120
100
140
120
100
140
120
100
80
60
40
20
80
60
40
20
80
60
40
20
0
0
0
0
0
0
MAX T
Figure 43. 300 mm
Figure 44. 100 mm
Figure 45. 0 mm
1mA
10mA
1mA
10mA
1mA
10mA
J
DO NOT OPERATE ABOVE THIS POINT
DO NOT OPERATE ABOVE THIS POINT
DO NOT OPERATE ABOVE THIS POINT
1
1
1
50mA
100mA
50mA
100mA
50mA
100mA
2
2
2
of PCB Copper, T
V
V
V
2
2
2
of PCB Copper, T
of PCB Copper, T
IN
IN
IN
– V
– V
– V
OUT
OUT
OUT
250mA
360mA
250mA
360mA
250mA
360mA
(V)
(V)
(V)
3
3
3
A
(LOAD CURRENT)
(LOAD CURRENT)
(LOAD CURRENT)
A
A
= 85°C
= 85°C
= 85°C
500mA
500mA
500mA
MAX T
4
4
4
MAX T
J
J
5
5
5
Rev. 0 | Page 15 of 20
PRINTED CIRCUIT BOARD LAYOUT
CONSIDERATIONS
The 8-lead MSOP package has the four GND pins fused together
internally, which enhances its thermal characteristics. Heat
dissipation from the package is increased by connecting as much
copper as possible to the four GND pins of the ADP1715/
ADP1716. From Table 5 it can be seen that a point of
diminishing returns eventually is reached, beyond which an
increase in the copper size does not yield additional heat
dissipation benefits.
Figure 46 shows a typical layout for the ADP1715/ADP1716.
The four GND pins are connected to a large copper pad. If a
second layer is available, multiple vias can be used to connect
them, increasing the overall copper area. The input capacitor
should be placed as close as possible to the IN and GND pins.
The output capacitor should be placed as close as possible to the
OUT and GND pins. 0603 or 0402 size capacitors and resistors
should be used to achieve the smallest possible footprint
solution on boards where area is limited.
GND (TOP)
GND (BOTTOM)
IN
C1
Figure 46. Example PCB Layout
EN
ADP1715/
ADP1716
ADP1715/ADP1716
C3
C2
R1
OUT
R2

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