LP55281RLEV National Semiconductor, LP55281RLEV Datasheet - Page 7

• Manufacturer Part Number: LP55281RLEV
• Description: BOARD EVAL FOR LP5528 RGB DRIVER
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LP55281RLEV

• Current - Output / Channel: 400mA
• Outputs And Type: 12, Non-Isolated
• Voltage - Output: 5.3V
• Features: USB Interface
• Voltage - Input: 2.7 ~ 5.5V
• Utilized Ic / Part: LP55281
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

I
LOGIC INTERFACE CHARACTERISTICS
Symbol
Logic Input SS/SDA, SI/A0, SCK/SCL, IF_SEL
V
V
I
f
Logic Input NRST
V
V
I
t
Logic Output SO
V
V
I
Logic Output SDA
V
ALED
I
SCK/SCL
I
NRST
L
IL
IH
IL
IH
OL
OH
OL
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation
of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions,
see the Electrical Characteristics tables.
Note 2: All voltages are with respect to the potential at the GND pins.
Note 3: Battery/Charger voltage should be above 6V no more than 10% of the operational lifetime.
Note 4: Voltage tolerance of LP55281 above 6.0V relies on fact that V
(ON) at all conditions, National Semiconductor
Note 5: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T
= 140°C (typ.)
Note 6: For detailed soldering specifications and information, please refer to National Semiconductor Application Note AN1112 : Micro SMD Wafer Level Chip
Scale Package or National Semiconductor Application Note AN1412 : Micro SMDxt Wafer Level Chip Scale Package.
Note 7: The Human Body Model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. MIL-STD-883 3015.7
Note 8: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be
derated. Maximum ambient temperature (T
dissipation of the device in the application (P
following equation: T
Note 9: Junction-to-Ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists,
special care must be paid to thermal dissipation issues in board design.
Note 10: Min and Max limits are guaranteed by design, test or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.
Note 11: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.
Note 12: V
Note 13: Data guaranteed by design
Note 14: When V
DDA
output is not recommended for external use.
ALED current
tolerance
Parameter
Input Low Level
Input High Level
Logic Input
Current
Clock Frequency
Input Low Level
Input High Level
Logic Input
Current
Reset Pulse Width
Output Low Level I
Output High Level I
Output Leakage
Current
Output Low Level I
IN
rises above V
A-MAX
= T
J-MAX-OP
OUT
+ V
- (θ
I
Condition
I
SPI Mode,
V
SPI Mode,
1.65V
V
I
1.65V
V
I
1.65V
V
SCHOTTKY
JA
ALED
2
SO
SO
SO
SO
SDA
C
DDIO > 1.8V
DDIO
DDIO
SO
A-MAX
x P
D-MAX
= 2 mA
= -3 mA
= -2 mA
= 3 mA
®
= 2.8V
= 3 mA
D-MAX
set to 13.2 mA
does not guarantee any parameters or reliability for this device.
) is dependent on the maximum operating junction temperature (T
> 1.8V
> 1.8V
≤
≤
≤
), and the junction-to-ambient thermal resistance of the part/package in the application (θ
, V
V
V
V
).
OUT
DDIO
DDIO
DDIO
(Note 13)
starts to follow the V
< 1.8V
< 1.8V
< 1.8V
DD1
and V
IN
7
DD2
voltage rise so that V
(2.8V) are available (ON) at all conditions. If V
OUT
= V
IN
- V
0.8*V
SCHOTTKY
J-MAX-OP
V
V
11.9
Min
-1.0
-1.0
DDIO
DDIO
-10
1.2
0.5
0.5
10
DDIO
J
-
-
= 125°C), the maximum power
= 160°C (typ.) and disengages at T
V
V
13.2
Typ
DDIO
DDIO
DD1
0.3
0.3
0.3
0.3
0.3
and V
-
-
0.2*V
DD2
JA
), as given by the
14.5
Max
+10
400
1.0
0.5
1.0
0.5
0.5
1.0
0.5
13
are not available
5
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DDIO
Units
MHz
MHz
kHz
mA
µA
µA
µA
µs
%
V
V
V
V
V
V
V
J