AS1324-AD EB austriamicrosystems, AS1324-AD EB Datasheet - Page 14

• Manufacturer Part Number: AS1324-AD EB
• Description: BOARD EVAL AS1324-AD
• Manufacturer: austriamicrosystems

Specifications of AS1324-AD EB

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Voltage - Output: 1.8V
• Current - Output: 600mA
• Voltage - Input: 2.7 ~ 5.5 V
• Regulator Topology: Buck
• Frequency - Switching: 1.5MHz
• Board Type: Fully Populated
• Utilized Ic / Part: AS1324-AD
• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption
• Power - Output: -

AS1324
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
9.6 Efficiency
The efficiency of a switching regulator is equivalent to:
For optimum design, an analysis of the AS1324 is needed to determine efficiency limitations and to determine design changes for improved
efficiency. Efficiency can be expressed as:
Where:
L
Although all dissipative elements in the circuit produce losses, those four main sources should be considered for efficiency calculation:
9.6.1 Input Voltage Quiescent Current Losses
The V
results in a small (<0.1%) loss that increases with V
load currents.
9.6.2 I²R Losses
Most of the efficiency loss at medium to high load currents are attributed to I²R loss, and are calculated from the resistances of the internal
switches (R
internal switches. Therefore, the series resistance looking into the SW pin is a function of both NMOS & PMOS R
cycle (DC) and can be calculated as follows:
The R
9.6.3 Switching Losses
The switching current is the sum of the control currents and the MOSFET driver. The MOSFET driver current results from switching the gate
capacitance of the power MOSFETs. If a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from V
ground. The resulting dQ/dt is a current out of V
Where: Q
The losses of the gate charges are proportional to V
9.6.4 Other Losses
Basic losses in the design of a system should also be considered. Internal battery resistances and copper trace can account for additional
efficiency degradations in battery operated systems. By making sure that C
switching frequency, the internal battery and fuse resistance losses can be minimized. C
losses generally account for less than 2% total additional loss.
9.7 Thermal Shutdown
Due to its high-efficiency design, the AS1324 will not dissipate much heat in most applications. However, in applications where the AS1324 is
running at high ambient temperature, uses a low supply voltage, and runs with high duty cycles (such as in dropout) the heat dissipated may
exceed the maximum junction temperature of the device.
As soon as the junction temperature reaches approximately 150ºC the AS1324 goes in thermal shutdown. In this mode the internal PMOS &
NMOS switch are turned off. The device will power up again, as soon as the temperature falls below +145°C again.
9.8 Checking Transient Response
The main loop response can be evaluated by examining the load transient response. Switching regulators normally take several cycles to
respond to a step in load current. When a load step occurs, V
Where:
ESR is the effective series resistance of C
ΔI
steady-state value. During this recovery time V
www.austriamicrosystems.com/DC-DC_Step-Down/AS1324
1
OUT
, L
2
IN
, L
DS(ON)
also begins to charge or discharge C
3
current is the DC supply current given in the electrical characteristics which excludes MOSFET driver and control currents. V
, etc. are the individual losses as a percentage of input power.
SW)
PMOS
for both MOSFETs can be obtained from the
and the external inductor (R
and Q
NMOS
are the gate charges of the internal MOSFET switches.
R
SW
OUT
L
OUT
= (R
). In continuous mode, the average output current flowing through inductor L is split between the
.
OUT
IN
, which generates a feedback error signal. The regulator loop then acts to return V
Efficiency = 100% – (L
DS(ON)PMOS
that is typically much larger than the DC bias current. In continuous mode:
IN
can be monitored for overshoot or ringing that would indicate a stability problem.
IN
I²R losses = I
Efficiency = (P
, even at no load. The V
I
GC
and thus their effects will be more visible at higher supply voltages.
V
DROP
= f(Q
Electrical Characteristics on page
OUT
)(DC) + (R
PMOS
= ΔI
OUT
immediately shifts by an amount equivalent to:
Revision 1.05
OUT
OUT
²(R
+ Q
1
/P
+ L
DS(ON)NMOS
x ESR
SW
NMOS
IN
IN
2
)100%
IN
+ R
has adequate charge storage and very low ESR at the given
+ L
quiescent current loss dominates the efficiency loss at very low
)
L
3
)
+ ...)
)(1 – DC)
IN
and C
4. Thus, to obtain I²R losses calculate as follows:
OUT
ESR dissipative losses and inductor core
DS(ON)
as well as the duty
OUT
IN
IN
(EQ 10)
(EQ 12)
(EQ 13)
current
(EQ 11)
to its
14 - 20
(EQ 8)
(EQ 9)
to