MAX17007EVKIT+ Maxim Integrated Products, MAX17007EVKIT+ Datasheet - Page 27

• Manufacturer Part Number: MAX17007EVKIT+
• Description: KIT EVAL FOR MAX17007
• Manufacturer: Maxim Integrated Products
• Series: Quick-PWM™r

Specifications of MAX17007EVKIT+

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 2, Non-Isolated
• Voltage - Output: 1.2V, 1.5V
• Current - Output: 12A, 12A
• Voltage - Input: 7 ~ 24V
• Regulator Topology: Buck
• Frequency - Switching: 270kHz, 330kHz
• Board Type: Fully Populated
• Utilized Ic / Part: MAX17007
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 4. Fault Protection and Shutdown Operation
When the feedback voltage drops below the undervolt-
age threshold, the controller immediately pulls PGOOD
low and triggers a 200µs one-shot timer. If the feed-
back voltage remains below the undervoltage fault
threshold for the entire 200µs, then the undervoltage
fault latch of the faulted SMPS is set and that SMPS
begins its shutdown sequence. When the internal target
voltage drops below 0.1V, the MAX17007/MAX17008
force DL low for the faulted SMPS. Toggle EN or cycle
V
restart the controller.
The undervoltage thresholds are -200mV for SMPS1
(fixed 1.05V and adjustable REFIN1), -200mV for
SMPS2 in preset mode (fixed 1.5V output), and -100mV
for SMPS2 in adjustable mode (0.7V feedback).
A UV fault on one side does not affect the other side.
The MAX17007/MAX17008 feature a thermal-fault pro-
tection circuit. When the junction temperature rises
above +160°C, a thermal sensor activates the fault
latch, pulls PGOOD low, and shuts down the controller.
Both DL and DH are pulled low. Toggle EN or cycle
V
after the junction temperature cools by 15°C.
Shutdown (EN_ = High to Low)
Output UVP (Latched)
Thermal Fault (Latched)
Output OVP (Latched)
V
V
V
CC
CC
CC
CC
CC
POR
UVLO Falling Edge
UVLO Rising Edge
power below V
power below V
MODE
Core Controllers for Notebook Computers
______________________________________________________________________________________
CC
Thermal-Fault Protection (T
CC
Undervoltage Protection (UVP)
POR to clear the fault latch and
POR to reactivate the controller
Dual and Combinable QPWM Graphics
Voltage soft-shutdown initiated. Error
amplifier target slowly ramped down to
GND.
Controller shuts down and internal target
slews down. Controller remains off until
EN_ toggled or V
Controller shuts down and the internal
target slews down. Controller remains off
until V
SMPS controller enabled (assuming EN_
pulled high).
SMPS inactive.
CC
rises back above UVLO threshold.
CONTROLLER STATE
CC
power cycled.
SHDN
)
Each SMPS of the MAX17007/MAX17008 is enabled
when its respective EN is driven high. On the first rising
EN, the reference powers up first. Once the reference
exceeds its undervoltage lockout (UVLO) threshold
(~ 60µs), the internal analog blocks are turned on and
masked by a 140µs one-shot delay in order to allow the
bias circuitry and analog blocks enough time to settle
to their proper states. With the control circuitry reliably
powered up, the PWM controller begins switching. The
second rising EN, if controlled separately, also has the
140µs one-shot delay before its first DH pulse.
Power-on reset (POR) occurs when V
approximately 3V, resetting the fault latch and preparing
the controller for operation. The V
inhibits switching until V
troller powers up the reference once the system enables
the controller, V
ven high. With the reference in regulation, the controller
ramps the output voltage to the target voltage with a
1.3mV/µs slew rate for SMPS1 and 0.65mV/µs for SMPS2.
If the V
assumes that there is not enough supply voltage to make
valid decisions. To protect the output from overvoltage
faults, the controller shuts down immediately and forces
a high-impedance output (DL and DH pulled low).
CC
DL_ low and DH_ low after soft-shutdown
completed, internal 10 discharge on CSL_
activated.
(T
DL_ immediately forced high, DH_ pulled low
(high-side MOSFET disabled).
DL_ low, DH_ low, internal 10 discharge on
CSL_ activated.
DL_, DH_ switching.
DL_ low.
voltage drops below 4.25V, the controller
CC
exceeds 4.25V, and either EN is dri-
0 1V )
CC
DRIVER STATE
rises above 4.25V. The con-
V
CC
POR and UVLO
CC
CC
UVLO circuitry
rises above
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