ISL6559EVAL2 Intersil, ISL6559EVAL2 Datasheet - Page 3

• Manufacturer Part Number: ISL6559EVAL2
• Description: EVALUATION BOARD 2 ISL6559
• Manufacturer: Intersil

Specifications of ISL6559EVAL2

• Main Purpose: Special Purpose DC/DC, VRM Supply
• Outputs And Type: 1, Non-Isolated
• Power - Output: 67.6W
• Voltage - Output: 1.3V
• Current - Output: 52A
• Voltage - Input: 5V, 12V
• Regulator Topology: Buck
• Frequency - Switching: 250kHz
• Board Type: Fully Populated
• Utilized Ic / Part: HIP6601, ISL6559
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

0V
0A
0V
0V
0A
quickly rises above the ISL6559 enable threshold, triggering
a soft-start interval. The switching frequency of the converter
is 250kHz, therefore the soft-start interval (SS Interval) is
approximately 8.3ms. VCORE does not move initially due to
the manner in which soft-start is implemented within the
controller. After a short delay, VCORE begins to ramp
linearly towards the DAC set point. Of note, the input current,
ICC12, also ramps slowly due to the controlled rise of the
output voltage.
About 4.3ms into the soft-start interval, VCORE passes
through the under-voltage threshold, UV. The under-voltage
threshold is defined as the DAC setting minus 350mV. Once
this threshold is surpassed, the internal pull down on the
PGOOD pin is released and the PGOOD LED indicator
changes to green.
Transient Response
The AMD Hammer desktop specification requires the VRD
to support loading at the processor pins from 0 to 52 amps
with a maximum load step of 20A. The transient slew rate is
defined as 30A/µs for this design. During a transient, the
core voltage is required to remain within the static window of
±50mV around the DAC setting. The on-board load
generator and a bench-top electronic load simulate these
conditions.
The OFS pin allows the user to positively offset the DAC
reference voltage by placing a correctly sized resistor, R7,
from this pin to ground. For this design, the resistor value is
3.24kΩ, which equates to a positive offset of approximately
20mV at no-load. Load-line regulation is supported by the
ISL6559. The average current of the three active channels
flows out of pin IDROOP. When this pin is connected to the
FB pin, this average current creates a voltage drop across
R4 (R
to the output current of the converter, and effectively creates
an output voltage droop with a steady-state value of
approximately 40mV, for this design.
FIGURE 2. SOFT-START INTERVAL WAVEFORMS
FB
in the data sheet). This voltage drop is proportional
UV
SS INTERVAL
1ms/DIV
3
VCORE, 500mV/DIV
ICORE, 20A/DIV
PGOOD, 5V/DIV
ICC12, 5A/DIV
EN, 2V/DIV
Application Note 1137
1.300V
52A
The leading edge transient response of the ISL6559EVAL2
to the aforementioned maximum load conditions is shown in
Figure 3. A bench-top electronic load draws 32A
continuously from the converter, while the on-board load
generator provides a 20A load step. The core voltage
immediately drops to a minimum of 1.265V in response to
the 20A step. The effective ESR of the aluminum electrolytic
output capacitors contributes to over 80% of the drop as the
output capacitors begin to support the core voltage. The
controller detects the new load level by the drop in output
voltage and responds by pushing the PWM signals wider.
Note the difference in pulse widths just before and as the
transient slews up to 52A. The inductor currents rapidly
increase to meet this new demand, supplying an increasing
portion of the load. While the inductor currents are slewing,
the bulk output capacitors are supplying the load. The
inductors assume a majority of the load current in about 6µs,
thereby reducing the bulk capacitance required to support
the transient.
10A
The steady-state phase-to-phase current matching is also
displayed in Figure 3. A major contributor to good phase-to-
phase current matching is layout. Each channel has a nearly
identical component layout with tight placement of the critical
components.
The electronic load is removed and the on-board load
generator alone applies a 20A step. Figure 4 shows the core
voltage, load current, channel inductor currents, and PWM
signals changing in response to the trailing edge of the
32A
20A
0V
0V
0V
PWM2, 10V/DIV
PWM3, 10V/DIV
PWM1, 10V/DIV
FIGURE 3. RISING EDGE TRANSIENT RESPONSE
5µs/DIV
LOAD CURRENT, 10A/DIV
VCORE, 50mV/DIV
I
L1
, 10A/DIV
I
L2
, 10A/DIV
I
L3
, 10A/DIV