POEPHYTEREV-I National Semiconductor, POEPHYTEREV-I Datasheet - Page 67
POEPHYTEREV-I
Manufacturer Part Number
POEPHYTEREV-I
Description
BOARD EVAL LM5072, DP83848I
Manufacturer
National Semiconductor
Series
PHYTER®r
Datasheets
1.DP83848IVVNOPB.pdf
(84 pages)
2.LM5072MHX-50NOPB.pdf
(26 pages)
3.DP83848C-MAU-EK.pdf
(18 pages)
Specifications of POEPHYTEREV-I
Main Purpose
Special Purpose DC/DC, Power Over Ethernet
Outputs And Type
1, Isolated
Power - Output
24W
Voltage - Output
3.3V
Current - Output
7.3A
Voltage - Input
39 ~ 57V
Regulator Topology
Flyback
Frequency - Switching
250kHz
Board Type
Fully Populated
Utilized Ic / Part
DP83848, LM5072
Lead Free Status / RoHS Status
Not applicable / Not applicable
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8.2.5 100 Mb/s MII Receive Timing
Note: RX_CLK may be held low or high for a longer period of time during transition between reference and recovered
clocks. Minimum high and low times will not be violated.
8.2.6 100BASE-TX Transmit Packet Latency Timing
Note: For Normal mode, latency is determined by measuring the time from the first rising edge of TX_CLK occurring after
the assertion of TX_EN to the first bit of the “J” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100
Mb/s mode.
T2.5.1
T2.5.2
Parameter
T2.6.1
Parameter
PMD Output Pair
RX_CLK
RXD[3:0]
RX_DV
RX_ER
RX_CLK High/Low Time
RX_CLK to RXD[3:0], RX_DV, RX_ER Delay 100 Mb/s Normal mode
TX_CLK to PMD Output Pair
Latency
TX_CLK
TX_EN
TXD
Description
T2.5.2
Description
T2.5.1
IDLE
100 Mb/s Normal mode
T2.6.1
67
Valid Data
100 Mb/s Normal mode
Notes
(J/K)
Notes
T2.5.1
DATA
Min
Min
16
10
Typ
6
Typ
20
Max
www.national.com
Max
24
30
Units
bits
Units
ns
ns
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