ISL6228EVAL3Z Intersil, ISL6228EVAL3Z Datasheet - Page 10

• Manufacturer Part Number: ISL6228EVAL3Z
• Description: EVALUATION BOARD FOR ISL6228
• Manufacturer: Intersil
• Series: Robust Ripple Regulator™ (R³)r

Specifications of ISL6228EVAL3Z

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 2, Non-Isolated
• Voltage - Output: 1.5V or 1.8V, 1.8V
• Current - Output: 8A, 8A
• Voltage - Input: 3.3 ~ 25V
• Regulator Topology: Buck
• Frequency - Switching: 270kHz, 300kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6228
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -

The ISL6228 monitors the OCSET pin and the VO pin
voltages. Once the OCSET pin voltage is higher than the VO
pin voltage for more than 10µs, the ISL6228 declares an OCP
fault. The value of R
Where:
For example, if I
R
Resistor R
to sense the inductor current. To sense the inductor current
correctly not only in DC operation, but also during dynamic
operation, the R-C network time constant R
needs to match the inductor time constant L/DCR. The value
of C
For example, if L is 1.5µH, DCR is 4.5mΩ, and R
9kΩ, the choice of C
Upon converter startup, capacitor C
To prevent false OCP, a 10µA current source flows out of the
VO pin during start up, generating a voltage drop on resistor
R
PGOOD pin goes high, the VO pin current source will
terminate.
When an OCP fault is declared, the PGOOD pin will pull
down to 30Ω and latch off the converter. The fault will remain
latched until the EN pin has been pulled below the falling EN
threshold voltage V
falling POR threshold voltage
Overvoltage Protection
The OVP fault detection circuit triggers after the FB pin voltage
is above the rising overvoltage threshold V
2µs. The FB pin voltage is 0.6V in normal operation. The rising
overvoltage threshold V
the FB pin voltage is above 116% x 0.6V = 0.696V, for more
than 2µs, an OVP fault is declared.
When an OVP fault is declared, the PGOOD pin will pull
down to 60Ω and latch-off the converter. The OVP fault will
remain latched until the EN pin has been pulled below the
falling EN threshold voltage V
below the falling POR threshold voltage
Although the converter has latched-off in response to an
OVP fault, the LGATE gate-driver output will retain the ability
to toggle the low-side MOSFET on and off, in response to
R
C
OCSET
O
OCSET
SEN
- R
- I
- DCR is the inductor DC resistance
, which has the same resistance as R
SEN
overcurrent setpoint
OCP circuit
OC
OCSET
=
is the output current threshold that will activate the
-----------------------------------------
R
is then written as Equation 7:
=
is R
OCSET
OCSET
I
-------------------------- -
OC
OCSET
10μA
(Ω) is the resistor used to program the
•
L
DCR
OC
•
and capacitor C
DCR
ENTHF
OCSET
is 20A and DCR is 4.5mΩ, the choice of
SEN
= 20A x 4.5mΩ/10µA = 9kΩ.
OVR
= 1.5µH/(9kΩ x 4.5mΩ) = 0.037µF.
or if V
is then written as Equation 6:
is typically 116%. That means if
10
ENTHF
V
VCC_THF
CC
SEN
SEN
has decayed below the
or if V
form an R-C network
V
.
initial voltage is 0V.
OCSET
OVR
VCC_THF
CC
OCSET
for more than
has decayed
. When
OCSET
C
.
SEN
(EQ. 6)
(EQ. 7)
is
ISL6228
the output voltage transversing the V
thresholds. The LGATE gate-driver will turn on the low-side
MOSFET to discharge the output voltage, protecting the
load. The LGATE gate-driver will turn off the low-side
MOSFET once the FB pin voltage is lower than the falling
overvoltage threshold V
overvoltage threshold V
the FB pin voltage falls below 106% x 0.6V = 0.636V, for
more than 2µs, the LGATE gate-driver will turn off the low-
side MOSFET. If the output voltage rises again, the LGATE
driver will again turn on the low-side MOSFET when the FB
pin voltage is above the rising overvoltage threshold V
for more than 2µs. By doing so, the ISL6228 protects the
load when there is a consistent overvoltage condition.
Undervoltage Protection
The UVP fault detection circuit triggers after the FB pin
voltage is below the undervoltage threshold V
than 2µs. The FB pin voltage is 0.6V in normal operation.
The undervoltage threshold V
means if the FB pin voltage is below 86% x 0.6V = 0.516V,
for more than 2µs, an UVP fault is declared, and the
PGOOD pin will pull down to 95Ω and latch-off the converter.
The fault will remain latched until the EN pin has been pulled
below the falling EN threshold voltage V
decayed below the falling POR threshold voltage
V
Programming the Output Voltage
When the converter is in regulation there will be 0.6V from
the FB pin to the GND pin. Connect a two-resistor voltage
divider across the VO pin and the GND pin with the output
node connected to the FB pin. Scale the voltage-divider
network such that the FB pin is 0.6V with respect to the GND
pin when the converter is regulating at the desired output
voltage. The output voltage can be programmed from 0.6V
to 5V.
Programming the output voltage is written as Equation 8:
Where:
Choose R
to Equation 9:
V
R
VCC_THF
REF
BOTTOM
- V
- The voltage to which the converter regulates the FB pin
- R
- R
is the V
from the FB pin to the converter output. In addition to
setting the output voltage, this resistor is part of the loop
compensation network
connects from the FB pin to the GND pin
O
TOP
BOTTOM
=
is the desired output voltage of the converter
V
O
TOP
.
is the voltage-programming resistor that connects
=
•
REF
-------------------------------------------------- -
R
V
---------------------------------- -
TOP
V
value first, and calculate R
REF
is the voltage-programming resistor that
O
R
–
BOTTOM
+
•
V
R
R
REF
TOP
BOTTOM
OVF
OVF
is typically 106%. That means if
for more than 2µs. The falling
UV
is typically 86%. That
OVR
ENTHF
BOTTOM
and V
UV
or if V
OVF
for more
according
May 7, 2008
CC
FN9095.2
(EQ. 8)
(EQ. 9)
OVR
has