ISL6228HIEVAL3Z Intersil, ISL6228HIEVAL3Z Datasheet - Page 13

• Manufacturer Part Number: ISL6228HIEVAL3Z
• Description: EVALUATION BOARD FOR ISL6228HI
• Manufacturer: Intersil
• Series: Robust Ripple Regulator™ (R³)r

Specifications of ISL6228HIEVAL3Z

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 2, Non-Isolated
• Voltage - Output: 1.05V or 1.2V, 1.2V
• Current - Output: 20A, 20A
• Voltage - Input: 3.3 ~ 25V
• Regulator Topology: Buck
• Frequency - Switching: 270kHz, 300kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6228
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -

As an example, suppose the high-side MOSFET has a total
gate charge Q
200mV. The calculated bootstrap capacitance is 0.125µF; for
a comfortable margin, select a capacitor that is double the
calculated capacitance. In this example, 0.22µF will suffice.
Use an X7R or X5R ceramic capacitor.
Layout Considerations
As a general rule, power should be on the bottom layer of
the PCB and weak analog or logic signals are on the top
layer of the PCB. The ground-plane layer should be adjacent
to the top layer to provide shielding. The ground plane layer
should have an island located under the IC, the
compensation components, and the FSET components. The
island should be connected to the rest of the ground plane
layer at one point.
Signal Ground and Power Ground
The bottom of the ISL6228 TQFN package is the signal
ground (GND) terminal for analog and logic signals of the IC.
Connect the GND pad of the ISL6228 to the island of ground
plane under the top layer using several vias, for a robust
thermal and electrical conduction path. Connect the input
capacitors, the output capacitors, and the source of the
lower MOSFETs to the power ground plane.
PGND (Pins 17 and 18)
This is the return path for the pull-down of the LGATE
low-side MOSFET gate driver. Ideally, PGND should be
connected to the source of the low-side MOSFET with a
low-resistance, low-inductance path.
VIN (Pins 2 and 5)
The VIN pin should be connected close to the drain of the
high-side MOSFET, using a low resistance and low
inductance path.
VCC (Pins 3 and 4)
For best performance, place the decoupling capacitor very
close to the VCC and GND pins.
PVCC (Pins 15 and 20)
For best performance, place the decoupling capacitor very
close to the PVCC and respective PGND pins, preferably on
the same side of the PCB as the ISL6228 IC.
FIGURE 8. TYPICAL POWER COMPONENT PLACEMENT
INDUCTOR
HIGH-SIDE
MOSFETS
GROUND
VIAS TO
g
PLANE
, of 25nC at V
PHASE
NODE
VOUT
GND
VIN
13
GS
OUTPUT
CAPACITORS
= 5V, and a ΔV
SCHOTTKY
DIODE
LOW-SIDE
MOSFETS
INPUT
CAPACITORS
BOOT
of
ISL6228
EN (Pins 11 and 24), and PGOOD (Pins 7 and 28)
These are logic signals that are referenced to the GND pin.
Treat as a typical logic signal.
OCSET (Pins 10 and 25)
The current-sensing network consisting of R
C
accurate measurement. Connect R
node side pad of the inductor, and connect C
output side pad of the inductor. Connect the OCSET pin to
the common node of node of R
FB (Pins 8 and 27), and VO (Pins 9 and 26)
The VO pin is used to sense the inductor current for OCP.
Connect the VO pin to the output-side of C
resistor R
place the voltage programming and loop compensation
components close to the VO, FB, and GND pins keeping the
high impedance trace short.
FSET (Pins 1 and 6)
This pin requires a quiet environment. The resistor R
and capacitor C
this pin. Keep fast moving nodes away from this pin.
LGATE (Pins 16 and 19)
The signal going through this trace is both high dv/dt and
high di/dt, with high peak charging and discharging current.
Route this trace in parallel with the trace from the PGND pin.
These two traces should be short, wide, and away from
other traces. There should be no other weak signal traces in
proximity with these traces on any layer.
BOOT (Pins 14 and 21), UGATE (Pins 13 and 22), and
PHASE (Pins 12 and 23)
The signals going through these traces are both high dv/dt
and high di/dt, with high peak charging and discharging
current. Route the UGATE and PHASE pins in parallel with
short and wide traces. There should be no other weak signal
traces in proximity with these traces on any layer.
Copper Size for the Phase Node
The parasitic capacitance and parasitic inductance of the
phase node should be kept very low to minimize ringing. It is
best to limit the size of the PHASE node copper in strict
accordance with the current and thermal management of the
application. An MLCC should be connected directly across
the drain of the upper MOSFET and the source of the lower
MOSFET to suppress the turn-off voltage spike.
SEN
needs to be connected to the inductor pads for
O
. The input impedance of the FB pin is high, so
FSET
should be placed directly adjacent to
OCSET
OCSET
and C
SEN
to the phase-
OCSET
SEN
SEN
through
.
to the
and
May 7, 2008
FSET
FN9095.2