ISL6562EVAL1 Intersil, ISL6562EVAL1 Datasheet - Page 4

• Manufacturer Part Number: ISL6562EVAL1
• Description: EVALUATION BOARD ISL6562
• Manufacturer: Intersil

Specifications of ISL6562EVAL1

• Main Purpose: Special Purpose DC/DC, VRM Supply
• Outputs And Type: 1, Non-Isolated
• Power - Output: 60W
• Voltage - Output: 1.5V
• Current - Output: 40A
• Voltage - Input: 5V, 12V
• Regulator Topology: Buck
• Frequency - Switching: 400kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6562
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Figure 10 shows a simplified diagram highlighting the critical
areas of a PC board layout. This diagram and the following
material represent goals to work towards during the layout
phase. Goals will be compromised during the layout process
due to component placement and space constraints. The
following text reviews these layout considerations in more
detail.
Current Sampling
1. Place the current sampling or sense resistor as close as
possible to the upper MOSFET drains. This is important
since the added inductance and resistance increase the
impedance and result in a reduction in drain voltage during
high peak pulse currents.
2. Current sense is critical, especially at lower current levels
where the current comparator threshold voltage is lower. A
good Kelvin connection requires that the voltage sample
must be taken at the R
planes that the resistor is connected.
3. The lines to the current sense resistor should be parallel
and run away from the PHASE or PWM signals to prevent
coupling of spikes to the current comparator input that may
delay or advance triggering of the comparator. Parallel rout-
ing will work towards equal exposure for both lines, so that
the comparator common mode rejection characteristic will
reduce the influence of coupled noise.
4. Place the current sense filter network near the controller.
This will help reduce extraneous inputs to the comparator.
PROCSSOR
VID CODES
12V
+V
INPUT
from
IN
FIGURE 10. SCHEMATIC DIAGRAM SHOWING ONLY ONE CHANNEL OF “IDEAL” COMPONENT PLACEMENT
{
{
SENSE
Next to IC
1
2
3
4
5
6
7
8
Locate
Parts
VID4
VID3
VID2
VID1
VID0
COMP
FB
CT
ISL6560
4
resistor ends and not at the
PWRGD
PWM1
PWM2
GND
VCC
REF
CS+
CS-
16
15
14
13
12
11
10
9
ISL6560/62 Evaluation Board
Locate
Parts
Next
to IC
Keep Leads Together
& Away from Output
1
2
3
4
UGATE
BOOT
PWM
GND
HIP6601ECB
Voltage Sampling
1. To obtain optimum regulation use the Kelvin connection
for the output voltage sample as shown on the Functional
System Schematic Diagram of Figure 10. The ground con-
nection, pin 9 of the ISL6560 should be connected to the
system ground at the load.
2. The two voltage sampling lines described in item 1 above
should also be routed away from any high current or high
pulse voltages such as the phase lines or pads. Doing this
will reduce the possibility of coupling undesired pulses into
the feedback signal and either modifying the output of the
error amplifier or, if of sufficient amplitude, spuriously trigger-
ing the current comparator by readjusting the threshold volt-
age.
Other Considerations
1. Keep the leads to the timing capacitor connected to pin
CT short and return the ground directly to pin 9.
2. When using a transistor to disable the converter by pulling
the CT pin to ground, place the transistor close to the CT pin
to minimize extraneous signal pickup.
3. As in all designs, keep decoupling networks near the pins
that must be decoupled. For example, the decoupling/filter
network on the FB input shown below. The series resistor
should be located next to the FB pin.
4. Large power and ground planes are critical to keeping
performance and efficiency high. Consider a 1mΩ resistance
in a 40A supply line. With 1.8V output, this results in slightly
over 2% power loss in a 72W supply.
PHASE
LGATE
PVCC
VCC
8
7
6
5
Try to return bypass
capacitors to ground
of lower MOSFETs
Place Near Drains of the
Output Transistors
+V
CORE