LP3906SQ-JXXIEV National Semiconductor, LP3906SQ-JXXIEV Datasheet - Page 10

• Manufacturer Part Number: LP3906SQ-JXXIEV
• Description: BOARD EVALUATION LP3906SQ-JXXI
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LP3906SQ-JXXIEV

• Main Purpose: DC/DC, Step Down with LDO
• Outputs And Type: 4, Non-Isolated
• Current - Output: 1.5A, 1.5A, 300mA, 300mA
• Regulator Topology: Buck
• Frequency - Switching: 2MHz
• Board Type: Fully Populated
• Utilized Ic / Part: LP3906
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Voltage - Output: -
• Voltage - Input: -
• Power - Output: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

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ENABLE CONFIGURATIONS THROUGH THE 20 PIN
HEADER
The following diagram shows how to enable or disable differ-
ent regulators by jumpering pins in the 20 pin header. One
practical use of grounding the enable pins of the regulators is
to signal a System Delay Sequence (EN_T). Using the Sys-
tem Delay Sequence is described in more detail in the
datasheet, but the basics are described below:
Jumper Settings to Disable All Regulators and EN_T
Top View of Header Connector
10
System Delay Sequence Information
•
•
•
EN_LDO1, EN_LDO2, EN_SW1, and EN_SW2 have
internal pullups and are by default ON.
The power-on sequence (EN_T) is internally pulled down,
and is by default OFF.
lf EN_T is connected to VDD or given a positive edge input
from 0 to VDD, the enable sequence will start.
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