SI3400-EVB Silicon Laboratories Inc, SI3400-EVB Datasheet - Page 12
![no-image](/images/manufacturer_photos/0/6/609/silicon_laboratories_inc_sml.jpg)
SI3400-EVB
Manufacturer Part Number
SI3400-EVB
Description
BOARD EVAL FOR SI3400
Manufacturer
Silicon Laboratories Inc
Type
PWM Controllersr
Datasheet
1.SI3400-E1-GM.pdf
(20 pages)
Specifications of SI3400-EVB
Mfg Application Notes
SI3400/01 High Power AppNote Si3400/1 PoE PD Controllers AppNote
Main Purpose
Special Purpose DC/DC, Power Over Ethernet
Outputs And Type
1, Non-Isolated
Voltage - Output
5V
Voltage - Input
44 ~ 57V
Regulator Topology
Buck
Frequency - Switching
350kHz
Board Type
Fully Populated
Utilized Ic / Part
Si3400
Input Voltage
5 V
Output Voltage
3.3 V
Interface Type
Ethernet
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Product
Power Management Modules
For Use With/related Products
Si3400
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Current - Output
-
Power - Output
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1352
SI3400-EVB
SI3400-EVB
Si3400/Si3401
The resistor values associated with each class are
shown in Table 10.
The 802.3 specification limits the classification time to
75 ms to limit the power dissipated in the PD. If the PSE
classification period exceeds 75 ms and the die
temperature rises above the thermal shutdown limits,
the thermal protection circuit will engage and disable
the classification current source in order to protect the
Si3400 and Si3401. The Si3400 and Si3401 stay in
classification mode until the input voltage exceeds 22 V
(the upper end of its classification operation region).
3.2.4. Under Voltage Lockout
The 802.3 standard specifies the PD to turn on when
the line voltage rises to 42 V and for the PD to turn off
when the line voltage falls to 30 V. The PD must also
maintain a large on-off hysteresis region to prevent
wiring losses between the PSE and the PD from
causing startup oscillation.
The Si3400 and Si3401 incorporate an undervoltage
lockout (UVLO) circuit to monitor the line voltage and
determine when to apply power to the integrated
switching regulator. Before the power is applied to the
switching regulator, the hotswap switch output (HSO)
pin is high-impedance and typically follows VPOS as
the input is ramped (due to the discharged switcher
supply capacitor). When the input voltage rises above
the UVLO turn-on threshold, the Si3400 and Si3401
begin to turn on the internal hotswap power MOSFET.
The switcher supply capacitor begins to charge up
under the current limit control of the Si3400 and Si3401,
and the HSO pin transitions from VPOS to VNEG. The
Si3400 and Si3401 include hysteretic UVLO circuits to
maintain power to the load until the input voltage falls
below the UVLO turn-off threshold. Once the input
voltage falls below 30 V, the internal hotswap MOSFET
is turned off.
12
Class
0
1
2
3
4
Reserved
Optional
Optional
Optional
Default
Usage
Table 10. Class Resistor Values
0.44 W to 12.95 W
6.49 W to 12.95 W
0.44 W to 3.84 W
3.84 W to 6.49 W
Power Levels
Reserved
Rev. 0.9
3.2.5. Dual Current Limit and Switcher Turn-On
The Si3400 and Si3401 implement dual current limits.
While the hotswap MOSFET is charging the switcher
supply capacitor, the Si3400 and Si3401 maintain a low
current limit. The switching regulator is disabled until the
voltage across the hotswap MOSFET becomes
sufficiently low, indicating the switcher supply capacitor
is almost completely charged. When this threshold is
reached, the switcher is activated, and the hotswap
current limit is increased. This threshold also has
hysteresis to prevent systemic oscillation as the
switcher begins to draw current and the current limit is
increased, which allows resistive losses in the cable to
effectively decrease the input supply.
The Si3400 and Si3401 stay in a high-level current limit
mode until the input voltage drops below the UVLO turn-
off threshold or excessive power is dissipated in the
hotswap switch. This dual level current limit allows the
system designer to design powered devices for use with
both legacy and compliant PoE systems.
An additional feature of the dual current limit circuitry is
foldback current limiting in the event of a fault condition.
When the current limit is switched to the higher level,
400 mA of current can be drawn by the PD. Should a
fault cause more than this current to be consumed, the
voltage across the hotswap MOSFET will increase to
clamp the maximum amount of power consumed. The
power dissipated by the MOSFET can be very high
under this condition. If the fault is very low impedance,
the voltage across the hotswap MOSFET will continue
to rise until the lower current limit level is engaged,
further reducing the dissipated power. If the fault
condition remains, the thermal overload protection
circuitry will eventually engage and shut down the
hotswap interface and switching regulator. The foldback
current limiting occurs much faster than the thermal
overload protection and is, therefore, necessary for
comprehensive protection of the hotswap MOSFET.
Nominal Class
10.5 mA
18.5 mA
Current
< 4 mA
28 mA
40 mA
RCL Resistor (1%,
(or open circuit)
> 1.33 kΩ
1/16 W)
69.8 Ω
45.3 Ω
30.9 Ω
127 Ω