LM2743-19AEVAL National Semiconductor, LM2743-19AEVAL Datasheet - Page 10

• Manufacturer Part Number: LM2743-19AEVAL
• Description: BOARD EVALUATION LM2743-19A
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LM2743-19AEVAL

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Voltage - Output: 1.2 ~ 3.3V
• Current - Output: 19A
• Voltage - Input: 8 ~ 14V
• Regulator Topology: Buck
• Frequency - Switching: 300kHz
• Board Type: Fully Populated
• Utilized Ic / Part: LM2743
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

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Application Information
THEORY OF OPERATION
The LM2743 is a voltage-mode, high-speed synchronous
buck regulator with a PWM control scheme. It is designed for
use in set-top boxes, thin clients, DSL/Cable modems, and
other applications that require high efficiency buck convert-
ers. It has output shutdown (SD), input under-voltage lock-out
(UVLO) mode and power good (PWGD) flag (based on over-
voltage and under-voltage detection). The over-voltage and
under-voltage signals are logically OR'ed to drive the power
good signal and provide a logic signal to the system if the
output voltage goes out of regulation. Current limit is achieved
by sensing the voltage V
START UP/SOFT-START
When V
logic high, the soft-start period begins. Then an internal, fixed
10 µA source begins charging the soft-start capacitor. During
soft-start the voltage on the soft-start capacitor C
nected internally to the non-inverting input of the error ampli-
fier. The soft-start period lasts until the voltage on the soft-
start capacitor exceeds the LM2743 reference voltage of
0.6V. At this point the reference voltage takes over at the non-
inverting error amplifier input. The capacitance of C
mines the length of the soft-start period, and can be
approximated by:
Where C
During soft start the Power Good flag is forced low and it is
released when the FB pin voltage reaches 70% of 0.6V. At
this point the chip enters normal operation mode, and the
output overvoltage and undervoltage monitoring starts.
NORMAL OPERATION
While in normal operation mode, the LM2743 regulates the
output voltage by controlling the duty cycle of the high side
and low side MOSFETs (see Typical Application Circuit). The
equation governing output voltage is:
The PWM frequency is adjustable between 50 kHz and 1 MHz
and is set by an external resistor, R
pin and ground. The resistance needed for a desired frequen-
cy is approximately:
Where f
TRACKING A VOLTAGE LEVEL
The LM2743 can track the output of a master power supply
during soft-start by connecting a resistor divider to the SS/
TRACK pin. In this way, the output voltage slew rate of the
LM2743 will be controlled by the master supply for loads that
CC
SW
SS
exceeds 2.76V and the shutdown pin (SD) sees a
is in Hz and R
is in µF and t
DS
SS
FADJ
across the low side MOSFET.
is in ms.
is in kΩ.
FADJ
, between the FREQ
SS
SS
is con-
deter-
10
require precise sequencing. When the tracking function is
used no soft-start capacitor should be connected to the SS/
TRACK pin. Otherwise, a C
the soft-start pin and ground should be used.
One way to use the tracking feature is to design the tracking
resistor divider so that the master supply’s output voltage
(V
bolically in
the power components) both rise together and reach their
target values at the same time. For this case, the equation
governing the values of the tracking divider resistors R
R
The current through R
precise tracking. The final voltage of the SS/TRACK pin
should be set higher than the feedback voltage of 0.6V (say
about 0.65V as in the above equation). If the master supply
voltage was 5V and the LM2743 output voltage was 1.8V, for
example, then the value of R
plies identical soft-start times would be 150Ω. A timing dia-
gram for the equal soft-start time case is shown in
T2
OUT1
is:
) and the LM2743’s output voltage (represented sym-
Figure 1
FIGURE 1. Tracking Circuit
as V
T1
OUT2
should be about 3 mA to 4 mA for
SS
T1
, i.e. without explicitly showing
value of at least 1 nF between
needed to give the two sup-
20095207
Figure
T1
and
2.