LM5001ISOEVAL National Semiconductor, LM5001ISOEVAL Datasheet - Page 9

• Manufacturer Part Number: LM5001ISOEVAL
• Description: BOARD EVALUATION LM5001ISO
• Manufacturer: National Semiconductor

Specifications of LM5001ISOEVAL

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Isolated
• Voltage - Output: 5V
• Current - Output: 1A
• Voltage - Input: 16 ~ 42V
• Regulator Topology: Flyback
• Frequency - Switching: 250kHz
• Board Type: Fully Populated
• Utilized Ic / Part: LM5001
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

ing begins. The controller remains enabled until VCC falls
below 2.7V or the EN pin falls below 1.16V.
An auxiliary supply voltage can be applied to the VCC pin to
reduce the IC power dissipation. If the auxiliary voltage is
greater than 6.9V, the internal regulator will essentially shut-
off, and internal power dissipation will be decreased by the
VIN voltage times the operating current. The overall converter
efficiency will also improve if the VIN voltage is much higher
than the auxiliary voltage. The externally applied VCC voltage
should not exceed 14V. The VCC regulator series pass MOS-
FET includes a body diode (see the Block Diagram) between
VCC and VIN that should not be forward biased in normal
operation. Therefore, the auxiliary VCC voltage should never
exceed the VIN voltage.
In high voltage applications extra care should be taken to en-
sure the VIN pin does not exceed the absolute maximum
voltage rating of 76V. Voltage ringing on the VIN line during
line transients that exceeds the Absolute Maximum Ratings
will damage the IC. Both careful PC board layout and the use
of quality bypass capacitors located close to the VIN and GND
pins are essential.
Oscillator
A single external resistor connected between RT and GND
pins sets the LM5001 oscillator frequency. To set a desired
oscillator frequency (F
sistor can be calculated from the following equation:
The tolerance of the external resistor and the frequency tol-
erance indicated in the Electrical Characteristics must be
taken into account when determining the worst case frequen-
cy range.
External Synchronization
The LM5001 can be synchronized to the rising edge of an
external clock. The external clock must have a higher fre-
quency than the free running oscillator frequency set by the
RT resistor. The clock signal should be coupled through a
100pF capacitor into the RT pin. A peak voltage level greater
than 2.6V at the RT pin is required for detection of the sync
pulse. The DC voltage across the RT resistor is internally
regulated at 1.5 volts. The negative portion of the AC voltage
of the synchronizing clock is clamped to this 1.5V by an am-
plifier inside the LM5001 with ~100Ω output impedance.
Therefore, the AC pulse superimposed on the RT resistor
must have positive pulse amplitude of 1.1V or greater to suc-
cessfully synchronize the oscillator. The sync pulse width
measured at the RT pin should have a duration greater than
SW
), the necessary value for the RT re-
9
15ns and less than 5% of the switching period. The sync pulse
rising edge initiates the internal CLK signal rising edge, which
turns off the power MOSFET. The RT resistor is always re-
quired, whether the oscillator is free running or externally
synchronized. The RT resistor should be located very close
to the device and connected directly to the RT and GND pins
of the LM5001.
Enable / Standby
The LM5001 contains a dual level Enable circuit. When the
EN pin voltage is below 450 mV, the IC is in a low current
shutdown mode with the VCC LDO disabled. When the EN
pin voltage is raised above the shutdown threshold but below
the 1.26V standby threshold, the VCC LDO regulator is en-
abled, while the remainder of the IC is disabled. When the EN
pin voltage is raised above the 1.26V standby threshold, all
functions are enabled and normal operation begins. An inter-
nal 6 µA current source pulls up the EN pin to activate the IC
when the EN pin is left disconnected.
An external set-point resistor divider from VIN to GND can be
used to determine the minimum operating input range of the
regulator. The divider must be designed such that the EN pin
exceeds the 1.26V standby threshold when VIN is in the de-
sired operating range. The internal 6 µA current source should
be included when determining the resistor values. The shut-
down and standby thresholds have 100 mV hysteresis to
prevent noise from toggling between modes. When the VIN
voltage is below 3.5VDC during start-up and the operating
temperature is below -20°C, the EN pin should have a pull-up
resistor that will provide 2 µA or greater current. The EN pin
is internally protected by a 6V Zener diode through a 1 kΩ
resistor. The enabling voltage may exceed the Zener voltage,
however the Zener current should be limited to less than 4mA.
Error Amplifier and PWM
Comparator
An internal high gain error amplifier generates an error signal
proportional to the difference between the regulated output
voltage and an internal precision reference. The output of the
error amplifier is connected to the COMP pin allowing the user
to add loop compensation, typically a Type II network, as il-
lustrated in Figure 1. This network creates a low frequency
pole that rolls off the high DC gain of the amplifier, which is
necessary to accurately regulate the output voltage.
F
pole. A zero provides phase boost near the closed loop unity
gain frequency, and a high frequency pole attenuates switch-
ing noise. The PWM comparator compares the current sense
signal from the current sense amplifier to the error amplifier
output voltage at the COMP pin.
DC_POLE
is the closed loop unity gain (0 dB) frequency of this
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