LM5001NISOEVAL National Semiconductor, LM5001NISOEVAL Datasheet - Page 4

• Manufacturer Part Number: LM5001NISOEVAL
• Description: BOARD EVALUATION FOR LM5001
• Manufacturer: National Semiconductor

Specifications of LM5001NISOEVAL

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Voltage - Output: 5V
• Current - Output: 1A
• Voltage - Input: 16 ~ 42V
• Regulator Topology: Flyback
• Frequency - Switching: 250kHz
• Board Type: Fully Populated
• Utilized Ic / Part: LM5001
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -
• Lead Free Status / Rohs Status: Not Compliant

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Since these equations don’t take into account the various
parasitic resistances and reactances present in all power
converters, there will be some difference between the calcu-
lated Bode plot and the gain and phase of the prototype
circuit. It is therefore important to measure the converter using
a network analyzer (Venable Instruments, Ridley Engineer-
ing, Agilent, etc.) to quantify the implementation and adjust
where appropriate.
LOOP COMPENSATION
The loop bandwidth and phase margin determines the re-
sponse to load transients, while insuring that the output noise
level meets the requirements. A common choice of loop unity
gain frequency is 5% of the switching frequency. This is sim-
ple to compensate, low noise and provides sufficient transient
response for most applications. The Plant Bode plot is exam-
ined for gain and phase at the desired Loop Unity Gain
Frequency and the compensator is designed to adjust the
loop gain and phase to meet the intended Loop Unity Gain
Frequency and phase margin (typically about 55°). When gain
is needed, the ratio of R8 and R9 sets the Error Amplifier to
provide the correct amount.
The phase margin is boosted by a transfer function zero at
frequency:
and a pole at:
The separation between F
amount of phase boost. If F
Unity Gain Frequency divided by a constant K, and F
the Loop Unity Gain Frequency times K, then the phase boost
provided at the Loop Unity Gain Frequency is:
The low frequency pole is determined by the Error Amplifier
open loop gain (A
VOL
) and R9, C9 and C10:
ZERO
ZERO
and F
is chosen to be the Loop
POLE
determines the
POLE
is
4
Optimal regulation is achieved by setting F
possible, but still permitting F
margin.
MOSFET RATING
The peak MOSFET current can be determined by:
Where η is the Flyback converter efficiency.
The power MOSFET must withstand the input voltage plus
the output voltage multiplied by the turns ratio during the off-
time.
In addition, any leakage inductance will cause a turn-off volt-
age spike above these two voltages. It will be controlled by
the MOSFET drain-to-source capacitance as well as other
parasitic capacitances. To further limit the spike magnitude,
an RCD termination such as R6, C7 and D2 or a Diode-Zener
clamp can be used.
DIODE RATING
The average diode current equals the output current under
normal circumstances, but the diode should be designed to
handle a continuous current limit condition for the worst case:
The maximum reverse voltage applied to the diode occurs
during the MOSFET on time:
The diode’s reverse capacitance will resonate with the trans-
former inductance (and other parasitic elements) to some
degree and cause ringing that may be a problem with con-
ducted and radiated emissions compliance. Usually an RC
snubber network will eliminate the ringing.
ZERO
to insure the desired phase
POLE(LO)
as high as