LM20333EVAL National Semiconductor, LM20333EVAL Datasheet - Page 13

• Manufacturer Part Number: LM20333EVAL
• Description: EVALUATION BOARD FOR THE LM20333
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LM20333EVAL

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Voltage - Output: 3.3V
• Current - Output: 3A
• Voltage - Input: 4.5 ~ 25V
• Regulator Topology: Buck
• Board Type: Fully Populated
• Utilized Ic / Part: LM20333
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -
• Frequency - Switching: -

If the desired solution differs from the table above the loop
transfer function should be analyzed to optimize the loop
compensation. The overall loop transfer function is the prod-
uct of the power stage and the feedback network transfer
functions. For stability purposes, the objective is to have a
loop gain slope that is -20dB/decade from a very low frequen-
cy to beyond the crossover frequency. Figure 3 shows the
transfer functions for power stage, feedback/compensation
network, and the resulting compensated loop for the
LM20333.
The power stage transfer function is dictated by the modula-
tor, output LC filter, and load; while the feedback transfer
function is set by the feedback resistor ratio, error amp gain
and external compensation network.
TABLE 2. Recommended Compensation for
V
12
12
12
12
12
12
FIGURE 3. LM20333 Loop Compensation
5
5
5
5
5
IN
C
OUT
= 150 µF, I
V
3.3
2.5
1.5
1.2
0.8
3.3
2.5
1.5
1.2
0.8
OUT
5
L (µH)
OUT
6.8
5.6
4.7
3.3
2.2
1.5
2.2
3.3
2.2
1.5
2
= 3A, f
R
C
30.9
33.2
40.2
22.1
18.2
8.45
38.3
38.3
30.1
18.2
SW
13
(kΩ) C
= 500kHz
C1
4.7
3.3
2.2
2.2
2.2
3.3
2.2
2.2
2.2
2.2
2.2
(nF)
30051672
13
To achieve a -20dB/decade slope, the error amplifier zero,
located at f
ter pole (f
Compensation of the LM20333 is achieved by adding an RC
network as shown in Figure 4 below.
A good starting value for C
Once the value of C
approximated using the equation below to cancel the output
filter pole (f
A higher crossover frequency can be obtained, usually at the
expense of phase margin, by lowering the value of C
recalculating the value of R
recalculating R
lower crossover frequency. As with any attempt to compen-
sate the LM20333 the stability of the system should be verified
for desired transient droop and settling time.
For low duty cycle operation, when the on time of the switch
node is less than 200ns, an additional capacitor (C
be added from the COMP pin to AGND. The recommended
value of this capacitor is 20pF. If low duty cycle jitter on the
switch node is observed, the value of this capacitor can be
increased to improve noise immunity; however, values much
larger than 100pF will cause the pole f
frequency degrading loop stability.
BOOT CAPACITOR (C
The LM20333 integrates an N-channel buck switch and as-
sociated floating high voltage level shift / gate driver. This gate
driver circuit works in conjunction with an internal diode and
an external bootstrap capacitor. A 0.1 µF ceramic capacitor,
connected with short traces between the BOOT pin and SW
pin, is recommended. During the off-time of the buck switch,
the SW pin voltage is approximately 0V and the bootstrap ca-
pacitor is charged from VCC through the internal bootstrap
diode.
SUB-REGULATOR BYPASS CAPACITOR (C
The capacitor at the VCC pin provides noise filtering for the
internal sub-regulator. The recommended value of C
should be no smaller than 0.1 µF and no greater than 1 µF.
The capacitor should be a good quality ceramic X5R or X7R
capacitor. In general, a 1 µF ceramic capacitor is recom-
mended for most applications. The VCC regulator should not
be used for other functions since it isn't protected against
short circuit.
FIGURE 4. Compensation Network for LM20333
P(FIL)
Z(EA)
P(FIL)
).
, should be positioned to cancel the output fil-
C1
) as shown in Figure 3.
will provide additional phase margin at a
C1
is chosen the value of RC should be
BOOT
C1
C1
)
for most applications is 2.2 nF.
. Likewise, increasing C
P2(EA)
30051645
to move to a lower
VCC
www.national.com
C2
)
) should
C1
C1
and
and
VCC