ADP1828LC-EVALZ Analog Devices Inc, ADP1828LC-EVALZ Datasheet - Page 27

• Manufacturer Part Number: ADP1828LC-EVALZ
• Description: BOARD EVALUATION ADP1828LC
• Manufacturer: Analog Devices Inc

Specifications of ADP1828LC-EVALZ

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Voltage - Output: 1.8V
• Current - Output: 5A
• Voltage - Input: 5.5 ~ 13.2V
• Regulator Topology: Buck
• Frequency - Switching: 600kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ADP1828
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -

A more accurate solution is to provide a divider from the
master voltage that sets the TRK pin voltage to be something
lower than 0.6 V at regulation, for example, 0.5 V. The slave
channel can be viewed as having a 0.5 V external reference
supplied by the master voltage. Keep in mind that PGOOD
is tripped when the TRK voltage is set to less than 0.55 V.
Once this is complete, the FB divider for the slave voltage is
designed as in the Compensating the Voltage Mode Buck
Regulator section except to substitute the 0.5 V reference
for the V
the master voltage is a function of the two dividers:
Figure 47 shows an example of ratiometric tracking circuit and
Figure 48 shows its voltage tracking waveforms.
C
Another option is to add another tap to the divider for the
master voltage. Split the R
two pieces, with the new tap at 0.5 V when the master voltage is
in regulation. This saves one resistor, but be aware that Type III
compensation on the master voltage causes the feedforward
signal of the master voltage to appear at the TRK input of the
slave channel.
1µF
SS
EN
SS
V
1
4
V
MASTER
CH1
CH3 1.00V
OUT
ADP1828
ADP1829
FB
Figure 47. An Example of a Ratiometric Tracking Circuit
OR
voltage. The ratio of the slave output voltage to
5.00V
FB
Figure 48. Ratiometric Tracking of Figure 47
=
⎛
⎜
⎜
⎝
⎛
⎜
⎜
⎝
1
1
B W
B W
+
+
CH2 1.00V
CH4 1.00V
R
R
EN FOR BOTH ADP1828
R
R
V
TRKT
TRKB
OUT_MASTER
TOP
BOT
BOT
3.3V
R
49.9kΩ
0.55V
R
10kΩ
TRKT
TRKB
⎞
⎟
⎟
⎠
150nF
⎞
⎟
⎟
⎠
V
resistor of the master voltage into
TRK_SLAVE
V
C
OUT_MASTER
OUT_SLAVE
B W
SS
M 100ms
ADP1828
EN
TRK
SS
FB
A CH1
2.60V
1.8V
V
OUT_SLAVE
R
22.6kΩ
R
10kΩ
TOP
BOT
(51)
Rev. C | Page 27 of 36
Figure 49 shows an example of DDR memory termination
application circuit, where the DDR memory termination voltage,
VTT, is ½ of VDDQ. VTT can sink current during the off cycle
of the ADP1828. The output waveform in Figure 50 shows that
VTT changes by one-half of the output change in VDDQ.
In addition, by selecting the resistor values in the divider carefully,
Equation 51 shows that the slave voltage output can be made to
have a faster ramp rate than that of the master voltage by setting
the TRK voltage at the slave larger than 0.6 V and R
than R
(that is, use a sufficiently large SS capacitor) such that the input
inrush current does not run into the current limit of the power
supply during startup.
C
1µF
SS
EN
SS
1
3
2
1
4
TRKT
Figure 50. DDR Termination; Output Waveforms of Figure 49
Figure 51. Ratiometric Tracking of Figure 47 with R
CH1
CH3 1.00V
CH1
CH3 500mV
ADP1828
ADP1829
. Make sure that the master SS period is long enough
Figure 49. An Example of a DDR Termination Circuit
OR
5.00V
500mV
FB
B W
B W
VDDQ (2.5V ± 0.25V, AC-COUPLED)
VTT (1.25V ± 0.125V, AC-COUPLED)
B W
B W
CH2 1.00V
CH4 1.00V
CH2 100mV
EN FOR BOTH ADP1828
VDDQ
2.5V
R
40.2kΩ
0.5V
R
10kΩ
TRKT
TRKB
V
150nF
V
OUT_MASTER
TRK_SLAVE
OUT_SLAVE
C
T
B W
B W
SS
M 100ms
M 200µs
TRK
ADP1828
EN
TRK
SS
A CH1
A CH1
FB
TRKT
ADP1828
50.0mV
TRKB
2.60V
= 5 kΩ
1.25V
VTT
greater
R
15kΩ
R
10kΩ
TOP
BOT