LM4947TLEVAL National Semiconductor, LM4947TLEVAL Datasheet - Page 25

• Manufacturer Part Number: LM4947TLEVAL
• Description: BOARD EVALUATION LM4947TL
• Manufacturer: National Semiconductor
• Series: Boomer®r

Specifications of LM4947TLEVAL

• Amplifier Type: Class D
• Output Type: 1-Channel (Mono) with Stereo Headphones
• Max Output Power X Channels @ Load: 1.19W x 1 @ 8 Ohm; 87mW x 2 @ 32 Ohm
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Board Type: Fully Populated
• Utilized Ic / Part: LM4947
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Application Information
I
SDA: This is the serial data input pin.
SCL: This is the clock input pin.
ID_ENB: This is the address select input pin.
I
The LM4947 uses a serial bus which conforms to the I
tocol to control the chip's functions with two wires: clock (SCL)
and data (SDA). The clock line is uni-directional. The data line
is bi-directional (open-collector). The maximum clock fre-
quency specified by the I
cussion, the master is the controlling microcontroller and the
slave is the LM4947.
The I
ID_ENB pin. The LM4947's two possible I
are of the form 111110X
is logic LOW; and X
interface is used to address a number of chips in a system,
the LM4947's chip address can be changed to avoid any pos-
sible address conflicts.
The bus format for the I
bus format diagram is broken up into six major sections:
The "start" signal is generated by lowering the data signal
while the clock signal is HIGH. The start signal will alert all
devices attached to the I
against their own address.
1. Bits MVC0 — MVC4 control 32 step volume control for MONO input
2. Bits LVC0 — LVC4 control 32 step volume control for LEFT input
3. Bits RVC0 — RVC4 control 32 step volume control for RIGHT input
4. Bits MC0 — MC2 control 8 distinct modes
5. Bits N3D3, N3D2, N3D1, N3D0 control programmable 3D function
6. N3D0 turns the 3D function ON (N3D0 = 1) or OFF (N3D0 = 0)
7. Bit OCL selects between SE with output capacitor (OCL = 0) or SE without output capacitors (OCL = 1). Default is OCL = 0
8. N3D1 selects between two different 3D configurations
9. SE/Diff-SE/Diff = 0 for SE mode; SE/Diff = 1 for Diff mode
2
2
Mono Volume Control
Right Volume Control
C PIN DESCRIPTION
C COMPATIBLE INTERFACE
Left Volume Control
Programmable 3D
ID_ADDR =
ID_ADDR =
Address
Mode Control
2
Chip
C address for the LM4947 is determined using the
0
1
1
A7
= 1, if ID_ENB is logic HIGH. If the I
1
1
1
2
2
1
C interface is shown in Figure 3. The
C bus to check the incoming address
0 (binary), where X
2
D7
C standard is 400kHz. In this dis-
0
0
1
1
1
A6
D6
1
1
1
0
1
0
1
1
2
(select)
(select)
C chip addresses
SE/Diff
1
L2R2
= 0, if ID_ADDR
D5
0
0
1
A5
TABLE 2. Control Registers
1
1
1
TABLE 1. Chip Address
L1R1 (select)
2
C pro-
MVC4
RVC4
LVC4
D4
2
0
C
A4
25
1
1
1
OCL (select)
The 8-bit chip address is sent next, most significant bit first.
The data is latched in on the rising edge of the clock. Each
address bit must be stable while the clock level is HIGH.
After the last bit of the address bit is sent, the master releases
the data line HIGH (through a pull-up resistor). Then the mas-
ter sends an acknowledge clock pulse. If the LM4947 has
received the address correctly, then it holds the data line LOW
during the clock pulse. If the data line is not held LOW during
the acknowledge clock pulse, then the master should abort
the rest of the data transfer to the LM4947.
The 8 bits of data are sent next, most significant bit first. Each
data bit should be valid while the clock level is stable HIGH.
After the data byte is sent, the master must check for another
acknowledge to see if the LM4947 received the data.
The "stop" signal ends the transfer. To signal "stop", the data
signal goes HIGH while the clock signal is HIGH. The data
line should be held HIGH when not in use.
I
The LM4947's I
I
level set by the I
that of the main power supply pin V
logic levels for the I
troller or microprocessor that is operating at a lower supply
voltage than the main battery of a portable system.
2
2
C INTERFACE POWER SUPPLY PIN (I
CV
MVC3
RVC3
N3D3
LVC3
D3
DD
pin. The LM4947's I
A3
1
1
1
2
2
CV
C interface is powered up through the
MVC2
RVC2
N3D2
LVC2
MC2
D2
2
DD
C interface are dictated by a microcon-
A2
0
0
0
pin which can be set independent to
2
C interface operates at a voltage
MVC1
RVC1
N3D1
LVC1
MC1
DD
D1
EC
A1
. This is ideal whenever
0
1
2
CV
DD
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)
MVC0
N3D0
RVC0
LVC0
MC0
A0
D0
0
0
0