MAX1110EVL11-DIP Maxim Integrated Products, MAX1110EVL11-DIP Datasheet - Page 20
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MAX1110EVL11-DIP
Manufacturer Part Number
MAX1110EVL11-DIP
Description
EVAL KIT FOR MAX1110
Manufacturer
Maxim Integrated Products
Specifications of MAX1110EVL11-DIP
Number Of Adc's
1
Number Of Bits
8
Sampling Rate (per Second)
50k
Data Interface
Serial
Inputs Per Adc
8 Single Ended
Input Range
0 ~ VREF
Power (typ) @ Conditions
0.23mW @ 50kSPS
Voltage Supply Source
Single Supply
Operating Temperature
0°C ~ 70°C
Utilized Ic / Part
MAX1110, MAX1112
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
20
TDFN
—
—
10
—
1
2
3
4
5
6
7
8
9
_____________________________________________________________________________________
AGND
*CONNECT EXPOSED PAD TO GROUND PLANE. DEVICES DO NOT OPERATE WHEN EP IS NOT CONNECTED TO GROUND!
AIN2
AIN1
V
REF
DD
TOP VIEW
1
2
3
4
5
µMAX
PIN
10
—
—
—
+
1
2
3
4
5
6
7
8
9
MAX11102
MAX11103
MAX11106
MAX11111
TDFN
SOT23
EP
—
—
—
—
—
—
3
2
1
6
5
4
EP*
CHSEL
NAME
AGND
OVDD
DOUT
SCLK
AIN1
AIN2
GND
GND
REF
V
AIN
CS
DD
10
9
8
7
6
SCLK
DOUT
OVDD
CHSEL
CS
Analog Input Channel 1. Single-ended analog input with respect to AGND with range
of 0V to V
Analog Input Channel 2. Single-ended analog input with respect to AGND with range
of 0V to V
Analog Input Channel. Single-ended analog input with respect to GND with range of
0V to V
Ground. Connect GND to the GND ground plane.
Analog Ground. Connect AGND directly the GND ground plane.
External Reference Input. REF defines the signal range of the input signal AIN1/AIN2:
0V to V
capacitor.
Positive Supply Voltage. Bypass V
range is 2.2V to 3.6V. For the SOT23 package, V
the input signal AIN: 0V to V
Active-Low Chip-Select Input. The falling edge of CS samples the analog input signal,
starts a conversion, and frames the serial data transfer.
Channel Select. Set CHSEL high to select AIN2 for conversion. Set CHSEL low to
select AIN1 for conversion.
Digital Interface Supply for SCLK, CS, DOUT, and CHSEL. The OVDD range is 1.5V
to V
Three-State Serial Data Output. ADC conversion results are clocked out on the falling
edge of SCLK, MSB first. See Figure 1.
Serial Clock Input. SCLK drives the conversion process. DOUT is updated on the fall-
ing edge of SCLK. See Figures 2 and 3.
Exposed Pad (TDFN and FMAX only). Connect EP directly to a solid ground plane.
Devices do not operate unless EP is connected to ground!
DD
. Bypass OVDD with a 10FF || 0.1FF capacitor to GND.
DD.
REF
REF
REF.
. The range of V
AGND
AIN1
AIN2
V
REF
.
DD
TOP VIEW
1
2
3
4
5
+
MAX11102
MAX11103
µMAX
REF
DD
.
is 1V to V
EP*
DD
FUNCTION
with a 10FF || 0.1FF capacitor to GND. V
10
9
8
7
6
DD.
SCLK
DOUT
OVDD
CHSEL
CS
Bypass REF to AGND with 10FF || 0.1FF
DD
also defines the signal range of
Pin Configurations
GND
V
AIN
DD
TOP VIEW
Pin Description
1
2
3
+
MAX11105
MAX11110
MAX11115
MAX11116
MAX11117
SOT23
6
5
4
CS
DOUT
SCLK
DD