ADC14DS105KARB/NOPB National Semiconductor, ADC14DS105KARB/NOPB Datasheet - Page 19

• Manufacturer Part Number: ADC14DS105KARB/NOPB
• Description: BOARD EVAL FOR ADC14DS105KARB
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC14DS105KARB/NOPB

• Design Resources: ADC14DS105KARB Ref Design
• Number Of Adc's: 2
• Number Of Bits: 14
• Sampling Rate (per Second): 105M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Power (typ) @ Conditions: 1W @ 105MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC14DS105
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC14DS105KARB

Functional Description
Operating on a single +3.3V supply, the ADC14DS105 digi-
tizes two differential analog input signals to 14 bits, using a
differential pipelined architecture with error correction circuitry
and an on-chip sample-and-hold circuit to ensure maximum
performance. The user has the choice of using an internal
1.2V stable reference, or using an external 1.2V reference.
Any external reference is buffered on-chip to ease the task of
driving that pin. Duty cycle stabilization and output data format
are selectable using the quad state function OF/DCS pin (pin
19). The output data can be set for offset binary or two's com-
plement.
Applications Information
1.0 OPERATING CONDITIONS
We recommend that the following conditions be observed for
operation of the ADC14DS105:
25 MHz
2.0 ANALOG INPUTS
2.1 Signal Inputs
2.1.1 Differential Analog Input Pins
The ADC14DS105 has a pair of analog signal input pins for
each of two channels. V
pair. The input signal, V
Figure 5 shows the expected input signal range. Note that the
common mode input voltage, V
V
mode level for the analog input signal. The positive peaks of
the individual input signals should each never exceed 2.6V.
Each analog input pin of the differential pair should have a
maximum peak-to-peak voltage of 1V, be 180° out of phase
with each other and be centered around V
peak voltage swing at each analog input pin should not ex-
ceed the 1V or the output data will be clipped.
CMO
2.7V
1.2V internal reference
V
V
REF
CM
2.7V
(pins 7,9) for V
= 1.5V (from V
≤
= 1.2V (for an external reference)
≤
FIGURE 5. Expected Input Signal Range
V
≤
f
A
CLK
V
≤
DR
≤
3.6V
≤
105 MHz
V
V
A
CM
CMO
IN
IN
= (V
will ensure the proper input common
IN
)
, is defined as
+ and V
IN
+) – (V
CM
IN
− form a differential input
, should be 1.5V. Using
IN
−)
CM
20211280
.The peak-to-
19
For single frequency sine waves the full scale error in LSB
can be described as approximately
Where dev is the angular difference in degrees between the
two signals having a 180° relative phase relationship to each
other (see Figure 6). For single frequency inputs, angular er-
rors result in a reduction of the effective full scale input. For
complex waveforms, however, angular errors will result in
distortion.
FIGURE 6. Angular Errors Between the Two Input Signals
It is recommended to drive the analog inputs with a source
impedance less than 100Ω. Matching the source impedance
for the differential inputs will improve even ordered harmonic
performance (particularly second harmonic).
Table 1indicates the input to output relationship of the AD-
C14DS105.
Will Reduce the Output Level or Cause Distortion
E
FS
= 16384 ( 1 - sin (90° + dev))
20211281
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