ADC14155HFEB/NOPB National Semiconductor, ADC14155HFEB/NOPB Datasheet - Page 15

• Manufacturer Part Number: ADC14155HFEB/NOPB
• Description: BOARD EVAL FOR ADC14155HF
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC14155HFEB/NOPB

• Number Of Adc's: 1
• Number Of Bits: 14
• Sampling Rate (per Second): 155M
• Data Interface: Parallel
• Inputs Per Adc: 1 Differential
• Power (typ) @ Conditions: 967mW @ 155MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC14155
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC14155HFEB

Functional Description
Operating on dual +3.3V and +1.8V supplies, the ADC14155
digitizes a differential analog input signal to 14 bits, using a
differential pipelined architecture with error correction circuitry
and an on-chip sample-and-hold circuit to ensure maximum
performance.
The user has the choice of using an internal 1.0V stable ref-
erence, or using an external reference. The ADC14155 will
accept an external reference between 0.9V and 1.1V (1.0V
recommended) which is buffered on-chip to ease the task of
driving that pin. The +1.8V output driver supply reduces pow-
er consumption and decreases the noise at the output of the
converter.
The quad state function pin CLK_SEL/DF (pin 8) allows the
user to choose between using a single-ended or a differential
clock input and between offset binary or 2's complement out-
put data format. The digital outputs are CMOS compatible
signals that are clocked by a synchronous data ready output
signal (DRDY, pin 34) at the same rate as the clock input. For
the ADC14155 the clock frequency can be between 5 MSPS
and 155 MSPS (typical) with fully specified performance at
155 MSPS. The analog input is acquired at the falling edge of
the clock and the digital data for a given sample is output on
the falling edge of the DRDY signal and is delayed by the
pipeline for 8 clock cycles. The data should be captured on
the rising edge of the DRDY signal.
Power-down is selectable using the PD pin (pin 7). A logic
high on the PD pin disables everything except the voltage
reference circuitry and reduces the converter power con-
sumption to 5 mW with no clock running. For normal opera-
tion, the PD pin should be connected to the analog ground
(AGND). A duty cycle stabilizer maintains performance over
a wide range of clock duty cycles.
Applications Information
1.0 OPERATING CONDITIONS
We recommend that the following conditions be observed for
operation of the ADC14155:
3.0V
V
V
5 MHz
1.0V internal reference
D
DR
= V
= 1.8V
≤
A
≤
V
Spectral Response @ 238 MHz Input
A
f
CLK
≤
3.6V
≤
155 MHz
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2.0 ANALOG INPUTS
2.1 Signal Inputs
2.1.1 Differential Analog Input Pins
The ADC14155 has one pair of analog signal input pins, V
+ and V
nal, V
Figure 2 shows the expected input signal range. Note that the
common mode input voltage, V
V
mode level for the analog input signal. The peaks of the indi-
vidual input signals should each never exceed 2.6V. Each
analog input pin of the differential pair should have a peak-to-
peak voltage equal to the reference voltage, V
out of phase with each other and be centered around
V
should not exceed the value of the reference voltage or the
output data will be clipped.
For single frequency sine waves the full scale error in LSB
can be described as approximately
Where dev is the angular difference in degrees between the
two signals having a 180° relative phase relationship to each
other (see Figure 3). For single frequency inputs, angular er-
rors result in a reduction of the effective full scale input. For
complex waveforms, however, angular errors will result in
distortion.
FIGURE 3. Angular Errors Between the Two Input Signals
It is recommended to drive the analog inputs with a source
impedance less than 100Ω. Matching the source impedance
RM
CM
0.9V
V
Will Reduce the Output Level or Cause Distortion
CM
.The peak-to-peak voltage swing at each analog input pin
(pin 45) for V
IN
= 1.5V (from V
, is defined as
≤
IN
FIGURE 2. Expected Input Signal Range
−, which form a differential input pair. The input sig-
V
REF
E
FS
≤
1.1V (for an external reference)
= 16384 ( 1 - sin (90° + dev))
CM
V
RM
IN
will ensure the proper input common
= (V
)
IN
+) – (V
CM
, should be 1.5V. Using
IN
−)
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REF
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, be 180°
IN