CLC5956PCASM National Semiconductor, CLC5956PCASM Datasheet - Page 10

• Manufacturer Part Number: CLC5956PCASM
• Description: EVALUATION BOARD FOR CLC5956
• Manufacturer: National Semiconductor

Specifications of CLC5956PCASM

• Number Of Adc's: 1
• Number Of Bits: 12
• Sampling Rate (per Second): 65M
• Data Interface: Parallel
• Inputs Per Adc: 1 Differential
• Input Range: 2.048 Vpp
• Power (typ) @ Conditions: 615mW @ 65MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: CLC5956
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *CLC5956PCASM

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Evaluation Printed Circuit Board
The Evaluation board for the CLC5956 allows for easy test
and evaluation of the product. The part may be ordered with
all components loaded and tested. The order number is the
CLC5956PCASM. The user supplies an analog input signal,
encode signal and power to the board and is able to take
latched 12-bit digital data out of the board.
ENCODE Input (ENC)
The ENCODE input is an SMA connector with a 50
nation. The signal is converted from single to differential and
its frequency is divided by four to produce a low jitter,
symmetrical encode signal for the CLC5956. The user
should provide a sinusoidal or square wave signal of 10 dBm
to 16 dBm amplitude at four times the converter’s desired
sample rate. It is recommended that the source be low jitter
to maintain best performance. The transformer will pass
signals in the 40 MHz to 260 MHz range which allows
sample rates of 10 Msps to 65 Msps.
Clock Option
The CLC5956 board is configured for a 4x clock input to
provide optimal performance with some (i.e., HP8662) syn-
thesizers. The HP8662 output has lower jitter above 160
MHz. Using a 208 MHz clock to sample at 52 MHz minimizes
the effect of the synthesizer on the measurement.
To use a 1x clock, replace the divide-by-4 sine-to-PECL
converter (U4, MC10EL33D) with an MC10EL16D. The
MC10EL16D sine-to-PECL converter does not divide the
clock. This approach would be suitable for use with a syn-
thesizer that has optimal jitter performance at 52 MHz (i.e.,
HP8643 or HP8644).
The best ADC performance is obtained with a low-jitter crys-
tal oscillator module installed at Y1 on the evaluation board.
U4 should be replaced with an MC10EL16D. Placing the
clock source on the evaluation board reduces ground loop
issues and thus improves performance.
Analog Input (AIN)
The analog input is an SMA connector with a 50
tion. The signal is converted from single to differential by a
transformer with a 5 MHz to 260 MHz bandwidth and ap-
proximately one dB loss. Full scale is approximately 11 dBm
or 2.2 V
input signal be low jitter, low noise and low distortion to allow
for proper test and evaluation of the CLC5956.
Supply Voltages (J1 pins 31 A&B
and 32 A&B)
The CLC5956PCASM is powered from a single 5V supply
connected from the referenced pins on the Eurocard con-
nector. The recommended supplies are low noise linear
supplies.
Digital Outputs (J1 pins 7A (MSB,
D11), 8B (D10) through 18B (LSB)
and 20B (Data Ready)
The digital outputs are provided on the Eurocard connector.
The outputs are buffered by 5V CMOS latches with 50
series output resistors. The rising edge of Data Ready may
be used to clock the output data into data collection cards or
PP
. It is recommended that the source for the analog
termina-
termi-
10
logic analyzers. The board has a location for the HP
01650-63203 termination adapter for HP 16500 logic analyz-
ers to simplify connection to the analyzer.
Minimum Conversion Rate
This ADC is optimized for high-speed operation. The internal
bipolar track and hold circuits will cause droop errors at low
sample rates. The point at which these errors cause a deg-
radation of performance is listed on the specifications page
as the minimum conversion rate. If a lower sample rate is
desired, the ADC should be clocked at a higher rate, and the
output data should be decimated. For example, to obtain a
10MSPS output, the ADC should be clocked at 20MHz, and
every other output sample should be used. No significant
power saving occurs at lower sample rates, since most of the
power is used in analog circuits rather than digital circuits.
CLC5957 and CLC5956
Interchangeability
The CLC5957 and CLC5956 12-bit, A/D converters are in-
terchangeable in applications when certain pinout require-
ments are met. It is important to note that the CLC5957
offers the following performance enhancements that are not
included in the CLC5956:
• Increased guaranteed sample rate over temperature to
• An internal PECL converter for the clock input so a wide
• A data valid output clock (DAV) to simplify the output
• The means to place the part in a shut-down state to
Due to these enhancements, some of the pin functions of the
CLC5957 and CLC5956 are different. Table 1 describes
these pin differences for each of the devices. Since the
CLC5957 and CLC5956 have the same package footprint,
the CLC5957 can be dropped in place of a CLC5956 if
certain pin connections are made. If full functionality of the
CLC5957 is desired when replacing the CLC5956, the board
layout for the CLC5956 will need to be modified with the
connections described in the ’CLC5957’ column of Table 1 . If
only CLC5956 functionality is to be retained when replacing
a CLC5956 with a CLC5957, then the board layout for the
CLC5956 should be modified with the connections described
in the ’Option’ column of Table 1 .
70MHz
range of AC-coupled differential signals can be used
interface
reduce power dissipation