ADC081S051EVAL National Semiconductor, ADC081S051EVAL Datasheet - Page 12

• Manufacturer Part Number: ADC081S051EVAL
• Description: BOARD EVALUATION FOR ADC081S051
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC081S051EVAL

• Number Of Adc's: 1
• Number Of Bits: 8
• Sampling Rate (per Second): 500k
• Data Interface: Serial
• Inputs Per Adc: 1 Single Ended
• Input Range: 0 ~ 5.25 V
• Power (typ) @ Conditions: 8.5mW @ 500kSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC081S051
• Lead Free Status / RoHS Status: Not applicable / Not applicable

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4.0 TYPICAL APPLICATION CIRCUIT
A typical application of the ADC is shown in
is provided in this example by the National Semiconductor
LP2950 low-dropout voltage regulator, available in a variety
of fixed and adjustable output voltages. The power supply pin
is bypassed with a capacitor network located close to the
ADC. Because the reference for the ADC is the supply volt-
age, any noise on the supply will degrade device noise per-
5.0 ANALOG INPUTS
An equivalent circuit of the ADC's input is shown in
Diodes D1 and D2 provide ESD protection for the analog in-
puts. At no time should the analog input go beyond (V
mV) or (GND − 300 mV), as these ESD diodes will begin to
conduct, which could result in erratic operation. For this rea-
son, the ESD diodes should not be used to clamp the input
signal.
The capacitor C1 in
is mainly the package pin capacitance. Resistor R1 is the on
resistance of the track / hold switch, and is typically 500Ω.
Capacitor C2 is the ADC sampling capacitor and is typically
26 pF. The ADC will deliver best performance when driven by
a low-impedance source to eliminate distortion caused by the
charging of the sampling capacitance. This is especially im-
portant when using the ADC to sample AC signals. Also
important when sampling dynamic signals is an anti-aliasing
filter.
6.0 DIGITAL INPUTS AND OUTPUTS
The ADC digital inputs (SCLK and CS) are not limited by the
same maximum ratings as the analog inputs. The digital input
pins are instead limited to +5.25V with respect to GND, re-
gardless of V
FIGURE 7. Equivalent Input Circuit
A
, the supply voltage. This allows the ADC to be
Figure 7
has a typical value of 4 pF, and
FIGURE 6. Typical Application Circuit
Figure
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6. Power
Figure
A
+ 300
7.
12
formance. To keep noise off the supply, use a dedicated linear
regulator for this device, or provide sufficient decoupling from
other circuitry to keep noise off the ADC supply pin. Because
of the ADC's low power requirements, it is also possible to
use a precision reference as a power supply to maximize per-
formance. The three-wire interface is shown connected to a
microprocessor or DSP.
interfaced with a wide range of logic levels, independent of
the supply voltage.
7.0 MODES OF OPERATION
The ADC has two possible modes of operation: normal mode,
and shutdown mode. The ADC enters normal mode (and a
conversion process is begun) when CS is pulled low. The de-
vice will enter shutdown mode if CS is pulled high before the
tenth falling edge of SCLK after CS is pulled low, or will stay
in normal mode if CS remains low. Once in shutdown mode,
the device will stay there until CS is brought low again. By
varying the ratio of time spent in the normal and shutdown
modes, a system may trade-off throughput for power con-
sumption, with a sample rate as low as zero.
7.1 Normal Mode
The fastest possible throughput is obtained by leaving the
ADC in normal mode at all times, so there are no power-up
delays. To keep the device in normal mode continuously,
CS must be kept low until after the 10th falling edge of SCLK
after the start of a conversion (remember that a conversion is
initiated by bringing CS low).
If CS is brought high after the 10th falling edge, but before the
16th falling edge, the device will remain in normal mode, but
the current conversion will be aborted, and SDATA will return
to TRI-STATE (truncating the output word).
Sixteen SCLK cycles are required to read all of a conversion
word from the device. After sixteen SCLK cycles have
elapsed, CS may be idled either high or low until the next
conversion. If CS is idled low, it must be brought high again
before the start of the next conversion, which begins when
CS is again brought low.
After sixteen SCLK cycles, SDATA returns to TRI-STATE.
Another conversion may be started, after t
by bringing CS low again.
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has elapsed,