ADC121S625EVAL/NOPB National Semiconductor, ADC121S625EVAL/NOPB Datasheet - Page 15

• Manufacturer Part Number: ADC121S625EVAL/NOPB
• Description: BOARD EVALUATION FOR ADC121S625
• Manufacturer: National Semiconductor

Specifications of ADC121S625EVAL/NOPB

• Number Of Adc's: 1
• Number Of Bits: 12
• Sampling Rate (per Second): 200k
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 2.25mW @ 200kSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC121S625
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC121S625EVAL

Functional Description
The ADC121S625 analog-to-digital converter uses a succes-
sive approximation register (SAR) architecture based upon
capacitive redistribution containing an inherent sample/hold
function.
ADC121S625 to acquire and convert an analog signal at
sample rates up to 200,000 conversions per second while
consuming very little power.
The ADC121S625 requires an external reference and exter-
nal clock, and a single +5V power source that can be as low
as +4.5V. The external reference can be any voltage be-
tween 100mV and 2.5V. The value of the reference voltage
determines the range of the analog input, while the reference
input current depends on the conversion rate.
The external clock can take on values as indicated in the
Electrical Characteristics Table of this data sheet. The duty
cycle of the clock is essentially unimportant, provided the
minimum clock high and low times are met. The minimum
clock frequency is set by internal capacitor leakage. Each
conversion requires 16 SCLK cycles to complete. Short
cycling can reduce this to 14 or 15 SCLK cycles, depending
upon whether the clock edge after the fall of CS is a rise or
a fall. See the timing diagrams.
The analog input is presented to the two input pins: +IN and
these pins is sampled on the internal capacitor array. The
inputs are disconnected from internal circuitry while a con-
version is in progress.
The digital conversion result is clocked out by the SCLK
input and is provided serially, most significant bit first, at the
D
that of the conversion currently in progress. It is possible to
continue to clock the ADC121S625 after the conversion is
complete and to obtain the serial data least significant bit
first. Each bit of the data word (including the leading null bit)
is clocked out on subsequent falling edges of SCLK and can
be clocked into the receiving device on the rising edges. See
the Digital Interface section and timing diagram for more
information.
1.0 REFERENCE INPUT
The externally supplied reference voltage sets the analog
input range. The ADC121S625 will operate with a reference
voltage in the range of 100mV to 2.5V. However, care must
be exercised when the reference voltage is less than 500
millivolts.
As the reference voltage is reduced, the range of input
voltages corresponding to each digital output code is re-
duced. That is, a smaller analog input range corresponds to
one LSB (Least Significant Bit). The size of one LSB is equal
to twice the reference voltage divided by 4096. When the
LSB size goes below the noise floor of the ADC121S625, the
noise will span an increasing number of codes and overall
noise performance will suffer. That is, for dynamic signals the
SNR will degrade and for d.c. measurements the code un-
certainty will increase. Since the noise is Gaussian in nature,
the effects of this noise can be reduced by averaging the
results of a number of consecutive conversions.
Additionally, since offset and gain errors are specified in
LSB, any offset and/or gain errors inherent in the A/D con-
verter will increase in terms of LSB size as the reference
voltage is reduced.
The ADC121S625 is more sensitive to nearby signals and
EMI (electromagnetic interference) when a low reference
–IN. Upon initiation of a conversion, the differential input at
OUT
pin. The digital data that is provided at the D
The
architecture
and
process
allow
OUT
pin is
the
15
voltage is used. For this reason, extra care should be exer-
cised in planning a clean layout, a low noise reference and a
clean power supply when using low reference voltages.
The reference input and the analog inputs are connected to
the capacitor array through a switch matrix when the input is
sampled. Hence, the only current required at the reference
and at the analog inputs is only a series of transient spikes.
The amount of these current spikes will depend, to some
degree, upon the conversion code, but will not vary a great
deal.
The current required to recharge the input capacitance at the
reference and analog signal inputs will cause voltage spikes
at these pins. Do not try to filter our these noise spikes.
Rather, ensure that the transient settles out during the
sample period (1.5 clock cycles after the fall at the CS input).
Lower reference voltages will decrease the current pulses at
the reference input and, therefore, will slightly decrease the
average input current there because the internal capaci-
tance is required to take on a lower charge at lower refer-
ence voltages. The reference current changes only slightly
with temperature. See the curves, “Reference Current vs.
Sample Rate”, “Reference Current vs. Temperature” and
“SNR vs. V
2.0 ANALOG SIGNAL INPUTS
The ADC121S625 has a differential input. As such, the ef-
fective input voltage that is digitized is (+IN) − (−IN). As is the
case with any differential input A/D converter, operation with
a fully differential input signal or voltage will provide better
performance than with a single-ended input. Yet, the
ADC121S625 can be presented with a single-ended input.
2.1 Differential Input Operation
With a fully differential input voltage or signal, a positive full
scale output code (0111 1111 1111b or 7FFh) will be obtained
when (+IN) − (−IN) ≥ V
scale code (1000 0000 0000b or 800h) will be obtained when
(+IN) − (−IN) ≤ −V
and linearity errors, which will affect the exact differential
input voltage that will determine any given output code.
2.2 Single-Ended Input Operation
For single-ended operation, the non-inverting input (+IN) of
the ADC121S625 should be driven with a signal or voltages
that have a maximum to minimum value range that is equal
to or less than twice the reference voltage. The inverting
input (−IN) should be biased to a stable voltage that is half
way between these maximum and minimum values. Note
that single-ended operation should only be used if the per-
formance degradation (compared with differential operation)
is acceptable.
2.3 Input Common Mode Voltage
The allowable input common mode voltage (V
depends upon the supply and reference voltages used for
the ADC121S625 and are depicted in Figure 1 and Figure 2.
The minimum and maximum common mode voltages for
differential and single-ended operation are shown in Table 1.
REF
” in the Typical Performance Curves section.
REF
+ 0.5 LSB. This ignores gain, offset
REF
− 1.5 LSB and a negative full
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CM
) range