ADC101S101EVAL National Semiconductor, ADC101S101EVAL Datasheet - Page 12

• Manufacturer Part Number: ADC101S101EVAL
• Description: BOARD EVALUATION FOR ADC101S101
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC101S101EVAL

• Number Of Adc's: 1
• Number Of Bits: 10
• Sampling Rate (per Second): 1M
• Data Interface: Serial
• Inputs Per Adc: 1 Single Ended
• Input Range: 0 ~ 5.25 V
• Power (typ) @ Conditions: 10mW @ 1MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC101S101
• Lead Free Status / RoHS Status: Not applicable / Not applicable

www.national.com
version and the start of another. At the maximum specified
SCLK frequency, the maximum guaranteed throughput is ob-
tained by using a 20 SCLK frame. As shown in
minimum allowed time between CS falling edges is deter-
mined by 1) 12.5 SCLKs for Hold mode, 2) the larger of two
quantities: either the minimum required time for Track mode
(t
or 1 SCLK padding to ensure an even number of SCLK cycles
so there is a falling SCLK edge when CS next falls. For ex-
ample, at the fastest rate for this family of parts, SCLK is
20MHz and 2.5 SCLKs are 125ns, so the minimum time be-
tween CS falling edges is calculated by
(12.5 SCLKs + t
maximum throughput of 1MSPS. At the slowest rate for this
family, SCLK is 1MHz. Using a 20 cycle conversion frame as
shown in Figure 2 yields a 20μs time between CS falling
4.0 TYPICAL APPLICATION CIRCUIT
A typical application of the ADC is shown in
is provided in this example by the National Semiconductor
LP2950 low-dropout voltage regulator, available in a variety
of fixed and adjustable output voltages. The power supply pin
is bypassed with a capacitor network located close to the
ADC. Because the reference for the ADC is the supply volt-
age, any noise on the supply will degrade device noise per-
ACQ
) or 2.5 SCLKs to finish reading the result and 3) 0, 1/2
12.5*50ns + 350ns + 0.5*50ns = 1000ns
ACQ
+ 1/2 SCLK) which corresponds to a
FIGURE 5. Ideal Transfer Characteristic
Figure
Figure
6. Power
2, the
12
edges for a throughput of 50KSPS. It is possible, however, to
use fewer than 20 clock cycles provided the timing parame-
ters are met. With a 1MHz SCLK, there are 2500ns in 2.5
SCLK cycles, which is greater than t
has come out, the clock will need one full cycle to return to a
falling edge. Thus the total time between falling edges of CS
is 12.5*1μs +2.5*1μs +1*1μs=16μs which is a throughput of
62.5KSPS.
3.0 ADC101S101 TRANSFER FUNCTION
The output format of the ADC is straight binary. Code transi-
tions occur midway between successive integer LSB values.
The LSB width for the ADC is V
characteristic is shown in
output code of 00 0000 0000 to a code of 00 0000 0001 is at
1/2 LSB, or a voltage of V
at steps of one LSB.
formance. To keep noise off the supply, use a dedicated linear
regulator for this device, or provide sufficient decoupling from
other circuitry to keep noise off the ADC supply pin. Because
of the ADC's low power requirements, it is also possible to
use a precision reference as a power supply to maximize per-
formance. The three-wire interface is shown connected to a
microprocessor or DSP.
A
/2048. Other code transitions occur
Figure
20145211
A
5. The transition from an
/1024. The ideal transfer
ACQ
. After the last data bit