CDB5364 Cirrus Logic Inc, CDB5364 Datasheet - Page 7

• Manufacturer Part Number: CDB5364
• Description: EVALUATION BOARD FOR CS5364
• Manufacturer: Cirrus Logic Inc

Specifications of CDB5364

• Number Of Adc's: 1
• Number Of Bits: 24
• Sampling Rate (per Second): 192k
• Data Interface: I²C, SPI™
• Inputs Per Adc: 4 Differential
• Power (typ) @ Conditions: 365mW @ 192kSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: CS5364
• Description/function: Audio A/D
• Operating Supply Voltage: 3.3 V
• Product: Audio Modules
• For Use With/related Products: CS5364
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant

DS625F4
SDOUT1/TDM
AIN2+, AIN2-
AIN4+, AIN4-
AIN3+, AIN3-
AIN1+, AIN1-
Pin Name
REF_GND
LRCK/FS
SDOUT2
MCLK
SCLK
TSTO
OVFL
FILT+
GND
TDM
XTO
VLC
RST
VLS
XTI
VQ
VD
VA
VX
Pin #
11,12
13,14
47,48
10,15
16,17
18,19
29,32
43,44
45,46
1,2
3,8
4,9
20
21
22
23
24
25
26
27
28
30
31
33
35
36
41
5
6
7
Differential Analog (Inputs) - Audio signals are presented differently to the delta sigma modula-
tors via the AIN+/- pins.
Ground (Input) - Ground reference. Must be connected to analog ground.
Analog Power (Input) - Positive power supply for the analog section.
Reference Ground (Input) - For the internal sampling circuits. Must be connected to analog
ground.
Positive Voltage Reference (Output) - Reference voltage for internal sampling circuits.
Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage.
Crystal Oscillator Power (Input) - Also powers control logic to enable or disable oscillator cir-
cuits.
Crystal Oscillator Connections (Input/Output) - I/O pins for an external crystal which may be
used to generate MCLK.
System Master Clock (Input/Output) - When a crystal is used, this pin acts as a buffered MCLK
Source (Output). When the oscillator function is not used, this pin acts as an input for the system
master clock. In this case, the XTI and XTO pins must be tied low.
Serial Audio Channel Clock (Input/Output)
In I²S mode, Serial Audio Channel Select. When low, the odd channels are selected.
In LJ mode, Serial Audio Channel Select. When high, the odd channels are selected.
In TDM Mode a frame sync signal. When high, it marks the beginning of a new frame of serial
audio samples. In Slave Mode, this pin acts as an input pin.
Main timing clock for the Serial Audio Interface (Input/Output) - During Master Mode, this pin
acts as an output, and during Slave Mode it acts as an input pin.
Test Out (Output) - Must be left unconnected.
Serial Audio Data (Output) - Channels 3,4.
Serial Audio Interface Power - Positive power for the serial audio interface.
Serial Audio Data (Output) - Channels 1,2.
TDM - TDM is complementary TDM data.
Digital Power (Input) - Positive power supply for the digital section.
Control Port Interface Power - Positive power for the control port interface.
Overflow (Output, open drain) - Detects an overflow condition on both left and right channels.
Reset (Input) - The device enters a low power mode when low.
Pin Description
CS5364
7