CDB5364 Cirrus Logic Inc, CDB5364 Datasheet - Page 3

• Manufacturer Part Number: CDB5364
• Description: EVALUATION BOARD FOR CS5364
• Manufacturer: Cirrus Logic Inc

Specifications of CDB5364

• Number Of Adc's: 1
• Number Of Bits: 24
• Sampling Rate (per Second): 192k
• Data Interface: I²C, SPI™
• Inputs Per Adc: 4 Differential
• Power (typ) @ Conditions: 365mW @ 192kSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: CS5364
• Description/function: Audio A/D
• Operating Supply Voltage: 3.3 V
• Product: Audio Modules
• For Use With/related Products: CS5364
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant

DS625DB1
1. CDB5364 SYSTEM OVERVIEW
The CDB5364 Evaluation Board provides an excellent means of quickly evaluating the CS5364. A digital audio in-
terface transmitter (CS8406) provides an easy interface to digital audio signal analyzers, including the majority of
digital audio test equipment. Standard analog input and digital output connectors are included for quick and reliable
board setup. An on-board FPGA is used for configuring the various modes of the CS5364. Graphical User Interface
software is supplied by Cirrus Logic, which allows programming the CDB5364 when connected to a host PC running
Microsoft Windows
2. QUICK-START GUIDE
This configuration provides a completely operational 24-bit Analog-to-Digital-Converter evaluation system. The
CS5364 is operating as a Master Device in Single Speed Mode with a 48 kHz sampling rate. Apply power and con-
nect analog input signals of 1 Vrms maximum (full scale) to the RCA inputs jacks. S/PDIF Digital audio data is avail-
able for evaluation at the Optical and Coaxial outputs.
3. DETAILED BOARD FEATURES
The CDB5364 Evaluation Board supports both the Stand-Alone and Control Port modes of the CS5364. An FPGA
(U2) controls digital signal routing between the CS5364, the CS8406 and the DSP I/O header. For user-friendly eval-
uation of the TDM interface, the FPGA will translate TDM data into PCM data and send it to the CS8406.
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Confirm that DIP switches S1 and S4 are in the closed (LO) position, pushed down to the right.
Connect the following jumpers.
Install a 12.288 MHz canned Oscillator to socket Y1, providing a Master Timing Clock for the system.
Install a jumper to J11 at the OSC position to enable the OSC drive buffer.
Connect power supply common to the GND binding post. Connect +5 V, +12 V and -12 V to the binding
posts as marked on the board silkscreen
Stand-Alone Evaluation
In Stand-Alone mode, the CDB5364 runs without an external PC attached. In this mode, the FPGA controls
operation of the board by dynamically reading DIP switches (S1 and S4) after a cold power-up or a push-
button board reset. Stand-Alone mode provides the most commonly used device settings. For additional
control of the CS5364, Control Port mode is used.
In Stand-Alone mode, as the DIP switches are repositioned, the FPGA simultaneously sets the appropriate
pins on the CS5364 and CS8406 to keep them synchronized with regard to sampling speed and data for-
mat.
– J7 - Install 5 jumpers to the left side of J7, enabling the DIP switches to operate correctly.
– J81, J95 - Install jumpers to these positions, grounding XTI and XTO of the CS5364.
– J1 - Install a jumper at the +5 V position, allowing VA to be supplied by the +5 V supply.
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CDB5364
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