AD9246-125EBZ Analog Devices Inc, AD9246-125EBZ Datasheet - Page 22

• Manufacturer Part Number: AD9246-125EBZ
• Description: BOARD EVAL FOR 125MSPS AD9246
• Manufacturer: Analog Devices Inc

Specifications of AD9246-125EBZ

• Design Resources: Using AD8376 to Drive Wide Bandwidth ADCs for High IF AC-Coupled Appls (CN0002) Driving AD9233/46/54 ADCs in AC-Coupled Baseband Appls (CN0051)
• Number Of Adc's: 1
• Number Of Bits: 14
• Sampling Rate (per Second): 125M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 2 Vpp
• Power (typ) @ Conditions: 458mW @ 125MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9246-125
• Silicon Manufacturer: Analog Devices
• Application Sub Type: ADC
• Kit Application Type: Data Converter
• Silicon Core Number: AD9246
• Kit Contents: Board
• Power Dissipation Pd: 458mW
• Input Channels Per Adc: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9246
TIMING
The lowest typical conversion rate of the AD9246 is 10 MSPS.
At clock rates below 10 MSPS, dynamic performance can degrade.
The AD9246 provides latched data outputs with a pipeline delay
of 12 clock cycles. Data outputs are available one propagation
delay (t
The length of the output data lines and the loads placed on
them should be minimized to reduce transients within the
AD9246. These transients can degrade the dynamic performance
of the converter.
Table 12. Output Data Format
Input (V)
VIN+ – VIN–
VIN+ – VIN–
VIN+ – VIN–
VIN+ – VIN–
VIN+ – VIN–
PD
) after the rising edge of the clock signal.
Condition (V)
< –VREF – 0.5 LSB
= –VREF
= 0
= +VREF – 1.0 LSB
> +VREF – 0.5 LSB
Binary Output Mode
00 0000 0000 0000
00 0000 0000 0000
10 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1111
Rev. A | Page 22 of 44
Data Clock Output (DCO)
The AD9246 provides a data clock output (DCO) intended for
capturing the data in an external register. The data outputs are valid
on the rising edge of DCO, unless the DCO clock polarity has
been changed via the SPI. See Figure 2 for a graphical timing
description.
Twos Complement Mode
10 0000 0000 0000
10 0000 0000 0000
00 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1111
Gray Code Mode
(SPI accessible)
11 0000 0000 0000
11 0000 0000 0000
00 0000 0000 0000
10 0000 0000 0000
10 0000 0000 0000
OR
1
0
0
0
1