MCP3551DM-PCTL Microchip Technology, MCP3551DM-PCTL Datasheet - Page 25

• Manufacturer Part Number: MCP3551DM-PCTL
• Description: BOARD DEMO FOR MCP3551
• Manufacturer: Microchip Technology
• Series: PICtail™r

Specifications of MCP3551DM-PCTL

• Number Of Adc's: 1
• Number Of Bits: 22
• Sampling Rate (per Second): 14
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 125°C
• Utilized Ic / Part: MCP3551
• Processor To Be Evaluated: MCP3551
• Interface Type: USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant

5.5
It is required that the microcontroller SPI port be
configured to clock out data on the falling edge of clock
and latch data in on the rising edge.
the operation shown in SPI mode 1,1, which requires
that the SCK from the MCU idles in the High state,
while
0,0, where the clock idles in the Low state. The
waveforms in the figures are examples of an MCU
operating the SPI port in 8-bit mode, and the
MCP3550/1/3 devices do not require data in 8-bit
groups.
FIGURE 5-6:
FIGURE 5-7:
© 2009 Microchip Technology Inc.
SDO/RDY
Receive
Buffer
MCU
SCK
Figure 5-7
CS
Using The MCP3550/1/3 with
Microcontroller (MCU) SPI Ports
SDO/RDY
Receive
Data stored into MCU
receive
transmission of first byte
DR
Buffer
DR
MCU
OH OL 21 20 19 18 17
SCK
CS
shows the similar case of SPI Mode
O O
H L
register
21 20 19 18 17
Data stored into MCU
receive
transmission of first byte
OL OH 21 20 19 18 17 16
SPI Communication – Mode 1,1.
SPI Communication – Mode 0,0.
D
R
O O
H L
after
register
21 20 19 18 17
Figure 5-6
16
Data
receive
transmission of second byte
after
16
15 14 13 12 11 10 9
15
stored
16
14 13 12 11 10 9
depicts
register
Data
receive
transmission of second byte
15 14 13 12 11 10 9
into
15 14 13 12 11 10 9
stored
MCU
after
register
into
In SPI mode 1,1, data is read using only 24 clocks or
three byte transfers. The data ready bit must be read
by testing the SDO/RDY line prior to a falling edge of
the clock.
In SPI mode 0,0, data is read using 25 clocks or four
byte transfers. Please note that the data ready bit is
included in the transfer as the first bit in this mode.
8
Data stored into MCU
receive
transmission of third byte
8
MCU
after
7
8
7
6
8
6 5 4 3 2
5
register
Data stored into MCU
receive
transmission of third byte
7
4
7 6 5 4 3 2 1
6
3 2
5
after
1
register
4
1
MCP3550/1/3
3 2
0
Data stored into MCU
receive
transmission of fourth byte
0
1
after
0
0
register
DS21950E-page 25
after