KDC2708CEVAL Intersil, KDC2708CEVAL Datasheet - Page 13

• Manufacturer Part Number: KDC2708CEVAL
• Description: DAUGHTER CARD FOR KAD2708
• Manufacturer: Intersil
• Series: FemtoCharge™r

Specifications of KDC2708CEVAL

• Number Of Adc's: 1
• Number Of Bits: 8
• Sampling Rate (per Second): 275M
• Data Interface: Parallel
• Inputs Per Adc: 1 Differential
• Input Range: 1.5 Vpp
• Power (typ) @ Conditions: 261mW @ 275MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: KAD2708C-27, KMB001 Motherboard
• For Use With: KMB001LEVAL - MOTHERBOARD FOR LVDS ADC CARD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Analog
Analog
A back-to-back transformer scheme is used to improve
common-mode rejection, which keeps the common-mode
level of the input matched to V
termination resistor should be determined based on the
desired impedance.
The sample and hold circuit design uses a switched
capacitor input stage, which creates current spikes when the
sampling capacitance is reconnected to the input voltage.
This creates a disturbance at the input which must settle
before the next sampling point. Lower source impedance will
result in faster settling and improved performance. Therefore
a 1:1 transformer and low shunt resistance are
recommended for optimal performance.
A differential amplifier can be used in applications that
require DC coupling, at the expense of reduced dynamic
performance. In this configuration the amplifier will typically
reduce the achievable SNR and distortion performance. A
typical differential amplifier configuration is shown in
Figure 25.
Input
+
FIGURE 23. TRANSFORMER INPUT, GENERAL APPLICATION
-
Vin
FIGURE 24. TRANSFORMER INPUT, HIGH IF APPLICATION
In
49.9O
Ω
1nF
1nF
0.01µF
FIGURE 25. DIFFERENTIAL AMPLIFIER INPUT
0.22µF
69.8O
ADT1-1WT
ADTL1-12
Ω
69.8O
100O
100O
Ω
Ω
Ω
ADTL1-12
ADT1-1WT
348O
348O
CM
13
Ω
Ω
CM
. The value of the
0.1µF
0.1µF
25O
25O
25O
25O
Ω
Ω
Ω
Ω
50O
151O
Ω
0.1µF
Ω
KAD2708
VCM
KAD2708
KAD2708
VCM
VCM
KAD2708C
Clock Input
The clock input circuit is a differential pair (see Figure 29).
Driving these inputs with a high level (up to 1.8V
input) sine or square wave will provide the lowest jitter
performance. The recommended drive circuit is shown in
Figure 26. The clock can be driven single-ended, but this will
reduce the edge rate and may impact SNR performance.
Clock
Use of the clock divider is optional. The KAD2708C's ADC
requires a clock with 50% duty cycle for optimum
performance. If such a clock is not available, one option is to
generate twice the desired sampling rate, then use the
KAD2708C's divide-by-2 to generate a 50%-duty-cycle
clock. This frequency divider uses the rising edge of the
clock, so 50% clock duty cycle is assured. Table 2 describes
the CLKDIV connection.
CLKDIV is internally pulled low, so a pull-up resistor or logic
driver must be connected for undivided clock.
Jitter
In a sampled data system, clock jitter directly impacts the
achievable SNR performance. The theoretical relationship
between clock jitter and maximum SNR is shown in
Equation 1 and is illustrated in Figure 27.
Where t
This relationship shows the SNR that would be achieved if
clock jitter were the only non-ideal factor. In reality,
achievable SNR is limited by internal factors such as
differential nonlinearity, aperture jitter and thermal noise.
Input
SNR
AVDD2
=
20 log
J
FIGURE 26. RECOMMENDED CLOCK DRIVE
CLKDIV PIN
is the RMS uncertainty in the sampling instant.
1nF
AVDD
AVSS
10
1kO
TABLE 2. CLKDIV PIN SETTINGS
TC4-1W
⎛
⎝
Ω
------------------- -
2πf
1
IN
t
J
⎞
⎠
1nF
1kO
Ω
DIVIDE RATIO
200O
2
1
PP
Ω
April 14, 2011
on each
FN6812.1
(EQ. 1)
CLKP
CLKN